Phase Locked Loop Using Delay Compensation Techniques. - Fulvio Spagna (ISCC, 2000)

An improved delay compensation technique for digital clock recovery loops. - Fulvio Spagna (ICECS, 2001)

A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS. - Lidong Chen; Xuguang Zhang; Fulvio Spagna (ISSCC, 2009)

A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS. - Fulvio Spagna; Lidong Chen; Mamatha Deshpande; Yongping Fan; Doug Gambetta; Sujatha Gowder; Sitaraman Iyer; Rohit Kumar; Peter Kwok; Renuka Krishnamurthy; Chien-chun Lin; Ravindran Mohanavelu; et al. (ISSCC, 2010)

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. - Sudeep Puligundla; Fulvio Spagna; Lidong Chen; Amanda Tran (ITC, 2010)

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS. - Shenggao Li; Fulvio Spagna; Ji Chen; Xiaoqing Wang; Luke Tong; Sujatha Gowder; Wenyan Jia; Roan Nicholson; Sitaraman Iyer; Rui Song; Lily Li; Meng-hung Chen; et al. (A-SSCC, 2018)

Clock and data recovery systems. - Fulvio Spagna (CICC, 2018)

A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol. - Mike Bichan; Clifford Ting; Bahram Zand; Jing Wang; Ruslana Shulyzki; James Guthrie; Katya Tyshchenko; Junhong Zhao; Alireza Parsafar; Eric Liu; Aynaz Vatankhahghadim; Shaham Sharifian; et al. (CICC, 2020)