A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. - Fumihiko Tachibana; Hironori Sato; Takahiro Yamashita; Hiroyuki Hara; Takeshi Kitahara; Shuou Nomura; Fumiyuki Yamane; Yoshiro Tsuboi; Keiko Seki; Shuuji Matsumoto; Yoshinori Watanabe; Mototsugu Hamada (CICC, 2008)

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. - Keiichi Kushida; Osamu Hirabayashi; Fumihiko Tachibana; Hiroyuki Hara; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Yuki Fujimura; Yusuke Niki; Miyako Shizuno; Shinichi Sasaki; Tomoaki Yabe (A-SSCC, 2011)

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. - Yusuke Niki; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Osamu Hirabayashi; Keiichi Kushida; Fumihiko Tachibana; Yuki Fujimura; Tomoaki Yabe (IEEE J. Solid State Circuits, 2011)

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. - Atsushi Kawasumi; Yasuhisa Takeyama; Osamu Hirabayashi; Keiichi Kushida; Fumihiko Tachibana; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe (ICICDT, 2012)

A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. - Atsushi Kawasumi; Yasuhisa Takeyama; Osamu Hirabayashi; Keiichi Kushida; Fumihiko Tachibana; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe (VLSIC, 2012)

A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. - Jun Deguchi; Fumihiko Tachibana; Makoto Morimoto; Masayoshi Chiba; Takeshi Miyaba; Hideki Tanaka; Kyoichi Takenaka; Satoshi Funayama; Kunihiko Amano; Kazuhide Sugiura; Ryuta Okamoto; Shouhei Kousai (ISSCC, 2013)

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. - Fumihiko Tachibana; Osamu Hirabayashi; Yasuhisa Takeyama; Miyako Shizuno; Atsushi Kawasumi; Keiichi Kushida; Azuma Suzuki; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe; Yasuo Unekawa (IEEE J. Solid State Circuits, 2014)

FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision. - Asuka Maki; Daisuke Miyashita; Kengo Nakata; Fumihiko Tachibana; Tomoya Suzuki; Jun Deguchi (A-SSCC, 2018)

A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems. - Yuta Tsubouchi; Daisuke Miyashita; Yuji Satoh; Takashi Toi; Fumihiko Tachibana; Makoto Morimoto; Junji Wadatsumi; Jun Deguchi (VLSI Circuits, 2018)

Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision. - Kengo Nakata; Asuka Maki; Daisuke Miyashita; Fumihiko Tachibana; Tomoya Suzuki; Jun Deguchi (ISCAS, 2019)

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. - Yuta Tsubouchi; Daisuke Miyashita; Takashi Toi; Yuji Satoh; Fumihiko Tachibana; Junji Wadatsumi; Makoto Morimoto; Ryuichi Fujimoto; Jun Deguchi (IEEE J. Solid State Circuits, 2019)

Weight Compression MAC Accelerator for Effective Inference of Deep Learning. - Asuka Maki; Daisuke Miyashita; Shinichi Sasaki; Kengo Nakata; Fumihiko Tachibana; Tomoya Suzuki; Jun Deguchi; Ryuichi Fujimoto (IEICE Trans. Electron., 2020)

Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN. - Kengo Nakata; Daisuke Miyashita; Asuka Maki; Fumihiko Tachibana; Shinichi Sasaki; Jun Deguchi; Ryuichi Fujimoto (AICAS, 2021)

A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (ESSCIRC, 2022)

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)