Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V. - Jürgen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (ISSCC, 2007)

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI. - Osamu Takahashi; Chad Adams; D. Ault; Erwin Behnen; O. Chiang; Scott R. Cottier; Paula K. Coulman; James Culp; Gilles Gervais; M. S. Gray; Y. Itaka; C. J. Johnson; et al. (ISSCC, 2008)

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V. - Juergen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (IEEE J. Solid State Circuits, 2008)

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kono; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (IEEE J. Solid State Circuits, 2016)

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. - Hiroshi Maejima; Kazushige Kanda; Susumu Fujimura; Teruo Takagiwa; Susumu Ozawa; Jumpei Sato; Yoshihiko Shindo; Manabu Sato; Naoaki Kanagawa; Junji Musha; Satoshi Inoue; Katsuaki Sakurai; et al. (ISSCC, 2018)

A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput. - Mario Sako; T. Nakajima; Fumihiro Kono; Takeshi Nakano; Masaki Fujiu; Junji Musha; Dai Nakamura; Naoaki Kanagawa; Yutaka Shimizu; Kosuke Yanagidaira; Tetsuaki Utsumi; T. Kawano; et al. (VLSI Technology and Circuits, 2023)