Switching activity analysis using Boolean approximation method. - Taku Uchino; Fumihiro Minami; Takashi Mitsuhashi; Nobuyuki Goto (ICCAD, 1995)

Switching activity analysis for sequential circuits using Boolean approximation method. - Taku Uchino; Fumihiro Minami; Masami Murakata; Takashi Mitsuhashi (ISLPED, 1996)

A low-power design method using multiple supply voltages. - Mutsunori Igarashi; Kimiyoshi Usami; Kazutaka Nogami; Fumihiro Minami; Yukio Kawasaki; Takahiro Aoki; Midori Takano; Chiharo Mizuno; Takashi Ishikawa; Masahiro Kanazawa; Shinji Sonoda; Makoto Ichida; et al. (ISLPED, 1997)

A Clock-Gating Method for Low-Power LSI Design. - Takeshi Kitahara; Fumihiro Minami; Toshiaki Ueda; Kimiyoshi Usami; Seiichi Nishio; Masami Murakata; Takashi Mitsuhashi (ASP-DAC, 1998)

Automated low-power technique exploiting multiple supply voltages applied to a media processor. - Kimiyoshi Usami; Mutsunori Igarashi; Fumihiro Minami; Takashi Ishikawa; Masahiro Kanazawa; Makoto Ichida; Kazutaka Nogami (IEEE J. Solid State Circuits, 1998)

Full-Chip Analysis Method of ESD Protection Network. - Sachio Hayashi; Fumihiro Minami; Masaaki Yamada (ISQED, 2004)

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. - Takeshi Kitahara; Naoyuki Kawabe; Fumihiro Minami; Katsuhiro Seta; Toshiyuki Furusawa (DATE, 2005)

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. - Takeshi Kitahara; Hiroyuki Hara; Shinichiro Shiratake; Yoshiki Tsukiboshi; Tomoyuki Yoda; Tetsuaki Utsumi; Fumihiro Minami (ASP-DAC, 2006)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

Gate Delay Estimation in STA under Dynamic Power Supply Noise. - Takaaki Okumura; Fumihiro Minami; Kenji Shimazaki; Kimihiko Kuwada; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations. - Susumu Kobayashi; Fumihiro Minami (IEICE Trans. Inf. Syst., 2013)