Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. - Fumiki Kato; Katsuya Kikuchi; Hiroshi Nakagawa; Masahiro Aoyagi (3DIC, 2011)

Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. - Katsuya Kikuchi; Fumiki Kato; Shunsuke Nemoto; Hiroshi Nakagawa; Masahiro Aoyagi; Youtaro Yasu; Kohji Koshiji (3DIC, 2013)

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. - Bui Thanh Tung 001; Xiaojin Cheng; Naoya Watanabe; Fumiki Kato; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

High-speed switching operation for a SiC CMOS and power module. - Atsushi Yao; Mitsuo Okamoto; Fumiki Kato; Hiroshi Hozoji; Shinji Sato; Shinsuke Harada; Hiroshi Sato (IEICE Electron. Express, 2021)