Time-varying signals analysis using squared analytic signals. - Fuminori Kobayashi; Hiroshi Suzuki (ICASSP, 1987)

Interpolative variable-speed repetitive control and its application to a deburring robot with cutting load control. - Yoichi Kimura; Ryoji Mukai; Fuminori Kobayashi; Masaru Kobayashi (Adv. Robotics, 1992)

A Digital PLL with Finite Impulse Responses. - Fuminori Kobayashi; Masayuki Haratsu (ISCAS, 1995)

Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's). - Fuminori Kobayashi; Masayuki Haratsu; Masateru Yabumoto; Michio Nakano (IEEE Trans. Ind. Electron., 1996)

An optically differential reconfigurable gate array and its power consumption estimation. - Minoru Watanabe; Fuminori Kobayashi (FPT, 2002)

An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. - Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2003)

Testing Method for Optical Connections Using Gate Array Structure in ORGAs. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2004)

Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2004)

A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. - Minoru Watanabe; Fuminori Kobayashi (FPL, 2004)

An optically differential reconfigurable gate array using a 0.18 μm CMOS process. - Minoru Watanabe; Fuminori Kobayashi (SoCC, 2004)

An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. - Minoru Watanabe; Fuminori Kobayashi (VLSI Design, 2004)

Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. - Mototsugu Miyano; Minoru Watanabe; Fuminori Kobayashi (FPT, 2005)

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. - Minoru Watanabe; Fuminori Kobayashi (FPT, 2005)

An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. - Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2005)

A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. - Minoru Watanabe; Fuminori Kobayashi (ISCAS (2), 2005)

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. - Mototsugu Miyano; Minoru Watanabe; Fuminori Kobayashi (ISVLSI, 2005)

An Improved Dynamic Optically Reconfigurable Gate Array. - Minoru Watanabe; Fuminori Kobayashi (ISVLSI, 2005)

Optically Reconfigurable Gate Arrays vs. ASICs. - Minoru Watanabe; Fuminori Kobayashi (APCCAS, 2006)

A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. - Minoru Watanabe; Fuminori Kobayashi (ARC, 2006)

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. - Minoru Watanabe; Fuminori Kobayashi (ASP-DAC, 2006)

Logic Synthesis and Place-and-Route Environment for ORGAs. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2006)

Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2006)

Differential Reconfiguration Architecture suitable for a Holographic Memory. - Minoru Watanabe; Mototsugu Miyano; Fuminori Kobayashi (ERSA, 2006)

A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. - Minoru Watanabe; Fuminori Kobayashi (FPL, 2006)

Power consumption advantage of a dynamic optically reconfigurable gate array. - Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2006)

An optically differential reconfigurable gate array with a holographic memory. - Minoru Watanabe; Mototsugu Miyano; Fuminori Kobayashi (IPDPS, 2006)

A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. - Minoru Watanabe; Fuminori Kobayashi (ASP-DAC, 2007)

272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. - Minoru Watanabe; Takenori Shiki; Fuminori Kobayashi (ERSA, 2007)

A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. - Rio Miyazaki; Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2007)

Holographic memory reconfigurable VLSI. - Minoru Watanabe; Fuminori Kobayashi (ISCAS, 2007)

Low-jitter PLL by interpolate compensation. - Yutaka Nakanishi; Fuminori Kobayashi; Hitoshi Kondoh (APCCAS, 2008)

MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. - Fuminori Kobayashi; Yasuyuki Morikawa; Minoru Watanabe (ERSA, 2008)

A PLL configuration for reducing both incoming and inherent jitters. - Fuminori Kobayashi; Yuhta Egashira; Hitoshi Kondoh (ICECS, 2009)

A motor speed control system using a hybrid of dual-loop PLL and feed-forward. - Hidekazu Machida; Michinobu Kambara; Kouta Tanaka; Fuminori Kobayashi (AMC, 2010)

Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory. - Takayuki Mabuchi; Minoru Watanabe; Akifumi Ogiwara; Fuminori Kobayashi (AHS, 2011)

Integrally accurate resolver-to-digital converter (RDC). - Nordinah Ismail; Fuminori Kobayashi; Manabu Inoue (ASCC, 2015)

Direct optical communication on an optically reconfigurable gate array. - Shinya Furukawa; Ili Shairah Abdul Halim; Minoru Watanabe; Fuminori Kobayashi (FGCT, 2016)

Analog Correlator by a Dynamically-Reconfigured Switched-Capacitor Circuit. - Fuminori Kobayashi (ISCAS, 2022)