Efficient placement and routing techniques for master slice LSI. - Hiroshi Shiraishi; Fumiyasu Hirose (DAC, 1980)

Logic Simulation System Using Simulation Processor (SP). - Minoru Saitoh; Kenji Iwata; Akiko Nokamura; Makoto Kakegawa; Junichi Masuda; Hirofumi Hamamura; Fumiyasu Hirose; Nobuaki Kawato (DAC, 1988)

A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. - Fumiyasu Hirose; Koichiro Takayama; Nobuaki Kawato (ITC, 1988)

Logic simulation engines in Japan. - Shigeru Takasaki; Fumiyasu Hirose; Akihiko Yamada (IEEE Des. Test, 1989)

Simulation processor "SP". - Hiroshi Yamada; Fumiyasu Hirose; Junichi Niitsuma; Tatsuya Shindo (Syst. Comput. Jpn., 1989)

A high-speed test-generation method using a test generation circuit. - Fumiyasu Hirose; Koichiro Takayama; Nobuaki Kawato (Syst. Comput. Jpn., 1990)

Performance Evaluation of an Event-Driven Logic Simulation Machine. - Fumiyasu Hirose (DAC, 1992)

Test pattern generation system for delay faults using a high speed simulation processor 'SP'. - Yukiko Izuta; Fumiyasu Hirose (VTS, 1992)

Automatic test program generation for pipelined processors. - Hiroaki Iwashita; Satoshi Kowatari; Tsuneo Nakata; Fumiyasu Hirose (ICCAD, 1994)

Panel: New Research Problems in the Emerging Test Technology. - Vishwani D. Agrawal; Bernard Courtois; Fumiyasu Hirose; Sandip Kundu; Chung-Len Lee; Yinghua Min; Parimal Pal Chaudhuri (Asian Test Symposium, 1995)

Logic synthesis for a single large look-up table. - Rajeev Murgai; Masahiro Fujita; Fumiyasu Hirose (ICCD, 1995)

CTL model checking based on forward state traversal. - Hiroaki Iwashita; Tsuneo Nakata; Fumiyasu Hirose (ICCAD, 1996)

Acceleration of mincut partitioning using hardware CAD accelerator TP5000. - Masahiro Sano; Shintaro Shimogori; Fumiyasu Hirose (ASP-DAC, 1997)

Acceleration of behavioral simulation on simulation specific machines. - Minoru Shoji; Fumiyasu Hirose; Shintaro Shimogori; Satoshi Kowatari; Hiroshi Nagai (ED&TC, 1997)

An approach to verify a large scale system-on-a-chip using symbolic model checking. - Koichiro Takayama; Taizo Satoh; Tsuneo Nakata; Fumiyasu Hirose (ICCD, 1998)

Speeding Up Look-up-Table Driven Logic Simulation. - Rajeev Murgai; Fumiyasu Hirose; Masahiro Fujita (VLSI, 1999)