A detailed router based on simulated evolution. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (ICCAD, 1988)

Routing using a pyramid data structure. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (ICCAD, 1989)

SILK: a simulated evolution router. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Data Path Construction and Refinement. - Fur-Shing Tsai; Yu-Chin Hsu (ICCAD, 1990)

Hybrid routing. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

STAR: An automatic data path allocator. - Fur-Shing Tsai; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Layout Modeling and Design Space Exploration in Pss1 System. - Fur-Shing Tsai; Yu-Chin Hsu (VLSI Design, 1997)

Post-routing timing optimization with routing characterization. - Chieh Changfan; Yu-Chin Hsu; Fur-Shing Tsai (ISPD, 1999)

Timing optimization on routed designs with incremental placementand routing characterization. - Chieh Changfan; Yu-Chin Hsu; Fur-Shing Tsai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. - Shi-Zheng Eric Lin; Chieh Changfan; Yu-Chin Hsu; Fur-Shing Tsai (ACM Trans. Design Autom. Electr. Syst., 2002)

Advanced techniques for RTL debugging. - Yu-Chin Hsu; Bassam Tabbara; Yirng-An Chen; Fur-Shing Tsai (DAC, 2003)

Visibility enhancement for silicon debug. - Yu-Chin Hsu; Fur-Shing Tsai; Wells Jong; Ying-Tsai Chang (DAC, 2006)

Bridging RTL and gate: correlating different levels of abstraction for design debugging. - Eric Cheung; Xi Chen 024; Fur-Shing Tsai; Yu-Chin Hsu; Harry Hsieh (HLDVT, 2007)