An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. - Yasuhiko Taito; Tetsushi Tanizaki; Mitsuya Kinoshita; Futoshi Igaue; Takeshi Fujino; Kazutami Arimoto (IEEE J. Solid State Circuits, 2003)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)