Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine. - Fuzhan Chen; Chongyun Zhang; Tianxin Min; Bo Xu; Quan Pan 002; C. Patrick Yue (ASICON, 2021)

An Integrated System Evaluation Engine for Cross-Domain Simulation and Design Optimization of High-Speed 5G Millimeter-Wave Wireless SoCs. - Weimin Shi; Fuzhan Chen; Xinyi Liu; Chongyun Zhang; Zilu Liu; Tianxin Min; Bo Xu; Li Wang; Jian Kang; C. Patrick Yue (ASICON, 2021)

A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS. - Shuo Feng; Fuzhan Chen; Zhenghao Li; Wentao Zhou; Dongfan Xu; Chun-Zhang Chen; Xuhui Liu; Hanming Wu; Quan Pan 002 (APCCAS, 2022)

A 56-Gb/s PAM-4 Transmitter Using Silicon Photonic Microring Modulator in 40nm CMOS. - Chongyun Zhang; Fuzhan Chen; C. Patrick Yue (MWSCAS, 2022)

A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS. - Fuzhan Chen; Chongyun Zhang; Li Wang 083; Quan Pan 002; C. Patrick Yue (ESSCIRC, 2023)

A Power-Efficient $ boldsymbol{4}- mathbf{V}_{ mathbf{ppd}}$ 128-Gb/s PAM-4 Optical Modulator Driver with Merged BV Doubler Topology in 130-nm BiCMOS. - Shuo Feng; Fuzhan Chen; Quan Pan 002 (ICTA, 2023)

A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOS. - Fuzhan Chen; C. Patrick Yue; Quan Pan 002 (CICC, 2024)

A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS. - Chongyun Zhang; Li Wang 083; Zilu Liu; Fuzhan Chen; Quan Pan 002; Xianbo Li; C. Patrick Yue (VLSI Technology and Circuits, 2024)

A 100Gbaud 4Vppd Distributed Linear Driver with Cross-Folded Transmission Lines and Cross-Coupled Gm Cells for Built-in 5-Tap FFE in 0.13µm SiGe BiCMOS. - Fuzhan Chen; C. Patrick Yue; Quan Pan 002 (ISSCC, 2025)