Optimizing Interconnect for Performance in Standard Cell Library. - Dharin Shah; Kothamasu Siva; G. Girishankar; N. S. Nagaraj (APCCAS, 2006)

Generating Scalable Polynomial Models: Key to Low Power High Performance Designs. - G. Girishankar; Shitanshu Tiwari (VLSI Design, 2006)

Design and technology interaction beyond 32nm. - Michael Clinton; Clive Bittlestone; G. Girishankar; Viet Le; Vinod Menezes (CICC, 2011)