Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. - Ravindranath Naiknaware; G. N. Nandakumar; Srinivasa Rao Kasa (ITC, 1993)

Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. - Ravindranath Naiknaware; G. N. Nandakumar; Rajeev Arora; John Larkin (VLSI Design, 1993)

False Path Detection at Transistor Level. - Abhijit Das; Samrat Sen; Mohan Rangan; Rupesh Nayak; G. N. Nandakumar (VLSI Design, 1998)

An Efficient Method to Generate Test Vectors for Combinational Cell Verification. - Nirav Patel; M. Srihari; Pooja Maheswari; G. N. Nandakumar (VLSI Design, 2004)

Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. - G. N. Nandakumar; Nirav Patel; Raghunatha Reddy; Makeshwar Kothandaraman (VLSI Design, 2005)

Generation of Test Vectors for Sequential Cell Verification - Santanu Bhowmick; Sanjay Bhattacherjee; G. N. Nandakumar (CoRR, 2011)