2-D Array processor having a controlled pipelined architecture for elliptical sparse matrices. - Costas E. Goutis; J. S. Sheblee; G. Russell (ICASSP, 1985)

CAD accelerators: A P Ambler, P Agrawal and W R Moore (Eds.) Elsevier, Netherlands (1991), 300 pp, ISBN 0444889647. - G. Russell (Comput. Aided Des., 1992)

A digital method for testing embedded switched capacitor filters. - M. Robson; G. Russell (EURO-DAC, 1996)

A 32-Bit Risc Processor with Concurrent Error Detection. - Ali Maamar; G. Russell (EUROMICRO, 1998)

ADOLT - An ADaptable On - Line Testing Scheme for VLSI Circuits. - Ali Maamar; G. Russell (DATE, 1999)

ASSEC: An Asynchronous Self-Checking RISC-based Processor. - Peter D. Hyde; G. Russell (DSD, 2004)

A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors. - Peter D. Hyde; G. Russell (IOLTS, 2004)