ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. - G. Surendra; S. K. Nandy 001; Paul Sathya (VLSI Design, 2001)

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. - G. Surendra; Subhasis Banerjee; S. K. Nandy 001 (Embedded Software for SoC, 2003)

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. - G. Surendra; Subhasis Banerjee; S. K. Nandy 001 (DATE, 2003)

On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. - G. Surendra; Subhasis Banerjee; S. K. Nandy 001 (Int. J. Parallel Program., 2003)

Exploiting program execution phases to trade power and performance for media workload. - Subhasis Banerjee; G. Surendra; S. K. Nandy 001 (ASP-DAC, 2004)

Power-performance trade-off using pipeline delays. - G. Surendra; Subhasis Banerjee; S. K. Nandy 001 (ASP-DAC, 2004)

On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. - G. Surendra; Subhasis Banerjee; S. K. Nandy 001 (WMPI, 2004)

Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. - G. Surendra; Subhasis Banerjee; S. K. Nandy 001 (J. Embed. Comput., 2006)

Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. - Subhasis Banerjee; G. Surendra; S. K. Nandy 001 (ASP-DAC, 2007)

On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. - Subhasis Banerjee; G. Surendra; S. K. Nandy 001 (J. Syst. Archit., 2008)