Ideas: a tool for VLSI CAD. - Alok Kumar; Vijeta Kashyap; Sunil D. Sherlekar; G. Venkatesh 001; S. Biswas; Anshul Kumar; P. C. P. Bhatt; Sashi Kumar (IEEE Des. Test, 1989)

A Methodology for Designing Optimal Self-Checking Sequential Circuits. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (ITC, 1991)

A methodology for the design of SFS/SCD circuits for a class of unordered codes. - Sandeep Pagey; Sunil D. Sherlekar; G. Venkatesh 001 (J. Electron. Test., 1991)

Path breaker: a tool for the optimal design of speed independent asynchronous controllers. - Yogesh Mishra; Sunil D. Sherlekar; G. Venkatesh 001 (EURO-DAC, 1992)

A Behavioral Fault Simulator For Ideal. - Ajay Khoche; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1992)

A Behavioral Fault Simulator for Ideal. - Ajay Khoche; Sunil D. Sherlekar; G. Venkatesh 001; Raja Venkateswaran (IEEE Des. Test Comput., 1992)

State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (VLSI Design, 1993)

Techniques for low power realization for FIR filters. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (ASP-DAC, 1995)

Synthesis of multiplier-less FIR filters with minimum number of additions. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (ICCAD, 1995)

A new methodology for the design of low-cost fail safe circuits and networks. - B. Ravi Kishore; Rubin A. Parekhji; Sandeep Pagey; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1995)

Concurrent Error Detection Using Monitoring Machines. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (IEEE Des. Test Comput., 1995)

Optimized Code Generation of Multiplication-free Linear Transforms. - Mahesh Mehendale; G. Venkatesh 001; Sunil D. Sherlekar (DAC, 1996)

Low power realization of FIR filters using multirate architectures. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1996)

Monitoring machine based synthesis technique for concurrent error detection in finite state machines. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (J. Electron. Test., 1996)

Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1997)

Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. - Mahesh Mehendale; Somdipta Basu Roy; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1998)

Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1998)

Extensions to Programmable DSP architectures for Reduced Power Dissipation. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1998)

Low-power realization of FIR filters on programmable DSPs. - Mahesh Mehendale; Sunil D. Sherlekar; G. Venkatesh 001 (IEEE Trans. Very Large Scale Integr. Syst., 1998)