Correspondence. - Gabor C. Temes (Comput. J., 1969)

An efficient procedure for the statistical transient analysis of switching circuits. - R. N. Gadenz; Gabor C. Temes (Comput. Aided Des., 1971)

Some applications of the adjoint network concept in frequency domain analysis and optimization. - Gabor C. Temes; R. M. Ebers; R. N. Gadenz (Comput. Aided Des., 1972)

Design Technique for Vestigial-Sideband Filters. - Henry John Orchard; Gabor C. Temes (IEEE Trans. Commun., 1974)

Real-factor FFT algorithms. - K. M. Cho; Gabor C. Temes (ICASSP, 1978)

A quasi-passive CMOS pipeline D/A converter. - Fong-Jim Wang; Gabor C. Temes; Simon Law (IEEE J. Solid State Circuits, 1989)

An 8-b 1.3-MHz successive-approximation A/D converter. - Khayrollah Hadidi; Vincent S. Tso; Gabor C. Temes (IEEE J. Solid State Circuits, 1990)

A first-order current-steering sigma-delta modulator. - Vittorio Comino; Michel S. J. Steyaert; Gabor C. Temes (IEEE J. Solid State Circuits, 1991)

Adaptive Digital Correction for Dual Quantization Sigma-Delta Modulators. - Sayfe Kiaei; Salem Abdennadher; Gabor C. Temes; Yaohua Yang (ISCAS, 1993)

High Speed Buffers for Op-amp Characterization. - Giri Rangan; John G. Kenney; Karthik Ramamurthy; Gabor C. Temes (ISCAS, 1993)

SC Circuits: The State of the Art Compared to SI Techniques. - Gabor C. Temes; Philippe Deval; Vlado Valencic (ISCAS, 1993)

A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements. - Mohammad Sarhang-Nejad; Gabor C. Temes (IEEE J. Solid State Circuits, 1993)

High-Linearity Calibration of Low-Resolution Digital-to-Analog Converters. - João Goes; José E. Franca; Nuno F. Paulino; Jorge A. Grilo; Gabor C. Temes (ISCAS, 1994)

A Novel Input Differential Pair for Improved Linearity Buffer and S/H Amplifier Design. - Khayrollah Hadidi; Gabor C. Temes (ISCAS, 1994)

A Dual-Quantization Multi-Bit Sigma Delta Analog/Digital Converter. - Armond Hairapetian; Gabor C. Temes (ISCAS, 1994)

ASP 12: Forum - Analog Electronics - a European Speciality? - Rudy J. van de Plassche; Bob Adams; Gerson A. S. Machado; Gabor C. Temes; Hugo De Man (ISCAS, 1994)

CMOS Circuits for On-Chip Capacitance Ratio Testing or Sensor Readout. - Yuming Cao; Gabor C. Temes (ISCAS, 1995)

High-Linearity Switched-Capacitor Circuits in Digital CMOS Technology. - Hirokazu Yoshizawa; Gabor C. Temes (ISCAS, 1995)

An enhanced slew rate source follower. - John G. Kenney; Giri Rangan; Karthik Ramamurthy; Gabor C. Temes (IEEE J. Solid State Circuits, 1995)

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization. - Christian C. Enz; Gabor C. Temes (Proc. IEEE, 1996)

Oversampling A/D and D/A converters. - Gabor C. Temes (EUSIPCO, 1998)

Predictive correlated double sampling switched-capacitor integrators. - Jorge A. Grilo; Gabor C. Temes (ICECS, 1998)

The use of predictive correlated double sampling techniques in low-voltage delta-sigma modulators. - Jorge A. Grilo; Gabor C. Temes (ICECS, 1998)

Offset- and gain-compensated track-and-hold stages. - Yunteng Huang; Gabor C. Temes; Paul F. Ferguson Jr. (ICECS, 1998)

High-accuracy circuits for on-chip capacitive ratio testing and sensor readout. - Bo Wang; Tetsuya Kajita; Tao Sun; Gabor C. Temes (IEEE Trans. Instrum. Meas., 1998)

Low-voltage switched-capacitor circuits. - E. Bidari; Mustafa Keskin; Franco Maloberti; Un-Ku Moon; Jesper Steensgaard; Gabor C. Temes (ISCAS (2), 1999)

Mismatch-shaping serial digital-to-analog converter. - Jesper Steensgaard; Un-Ku Moon; Gabor C. Temes (ISCAS (2), 1999)

Capacitor mismatch error cancellation technique for a successive approximation A/D converter. - Zhiliang Zheng; Un-Ku Moon; Jesper Steensgaard; Bo Wang; Gabor C. Temes (ISCAS (2), 1999)

Digital techniques for improving the accuracy of data converters. - Un-Ku Moon; Gabor C. Temes; Jesper Steensgaard (IEEE Commun. Mag., 1999)

MOSFET-only switched-capacitor circuits in digital CMOS technology. - Hirokazu Yoshizawa; Yunteng Huang; Paul F. Ferguson Jr.; Gabor C. Temes (IEEE J. Solid State Circuits, 1999)

A highly linear low-power 10 bit DAC for GSM. - Paul F. Ferguson Jr.; Xavier Haurie; Gabor C. Temes (CICC, 2000)

Improved adaptive digital compensation for cascaded ΔΣ ADCs. - Peter Kiss; José Silva 002; Un-Ku Moon; John T. Stonick; Gabor C. Temes (ISCAS, 2000)

A switched-capacitor DAC with analog mismatch correction. - Un-Ku Moon; José Silva 002; Jesper Steensgaard; Gabor C. Temes (ISCAS, 2000)

Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages. - Lei Wu; Mustafa Keskin; Un-Ku Moon; Gabor C. Temes (ISCAS, 2000)

Efficient error-cancelling algorithmic ADC. - Zhilliang Zheng; Byung-Moo Min; Un-Ku Moon; Gabor C. Temes (ISCAS, 2000)

Low-voltage low-sensitivity switched-capacitor bandpass Sigma-Delta modulator. - Mustafa Keskin; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2001)

Multibit Sigma-Delta ADC with mixed-mode DAC error correction. - Peter Kiss; Un-Ku Moon; Jesper Steensgaard; John T. Stonick; Gabor C. Temes (ISCAS (1), 2001)

Area efficient CMOS charge pump circuits. - Ryan Perigny; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2001)

Digital techniques for improved ΔΣ data conversion. - José Silva 002; Xuesheng Wang; Peter Kiss; Un-Ku Moon; Gabor C. Temes (CICC, 2002)

Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop. - Arun Rao; William McIntyre; J. Parry; Un-Ku Moon; Gabor C. Temes (ISCAS (4), 2002)

Digital correlation technique for the estimation and correction of DAC errors in multibit mash Delta-Sigma ADCs. - X. Wang; Un-Ku Moon; M. Liu; Gabor C. Temes (ISCAS (4), 2002)

A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps. - Mustafa Keskin; Un-Ku Moon; Gabor C. Temes (IEEE J. Solid State Circuits, 2002)

A two-chip interface for a MEMS accelerometer. - Tetsuya Kajita; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Instrum. Meas., 2002)

A Noise-shaping Accelerometer Interface Circuit for Two-chip Implementation. - Tetsuya Kajita; Un-Ku Moon; Gabor C. Temes (VLSI Design, 2002)

Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs. - Xuesheng Wang; Yuhua Guo; Un-Ku Moon; Gabor C. Temes (CICC, 2004)

Low-distortion delta-sigma topologies for MASH architectures. - José B. Silva; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2004)

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications. - Shelly Xiao; José B. Silva; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2004)

Theory and applications of incremental ΔΣ converters. - János Márkus; José B. Silva; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

An efficient ΔΣ ADC architecture for low oversampling ratios. - János Márkus; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

In Memoriam. - Alan N. Willson Jr.; Gabor C. Temes; Asad A. Abidi (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 μV DC offset. - Vincent Quiquempoix; Philippe Deval; Alexandre Barreto; Gabriele Bellini; Jerry Collings; János Márkus; José B. Silva; Gabor C. Temes (ESSCIRC, 2005)

A 10-bit algorithmic A/D converter for cytosensor application. - Thirumalai Rengachari; Vivek Sharma; Gabor C. Temes; Un-Ku Moon (ISCAS (6), 2005)

A generic multilevel multiplying D/A converter for pipelined ADCs. - Vivek Sharma; Un-Ku Moon; Gabor C. Temes (ISCAS (6), 2005)

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. - Gil-Cho Ahn; Dong-Young Chang; Matthew E. Brown; Naoto Ozaki; Hiroshi Youra; Ken Yamamura; Koichi Hamashita; Kaoru Takasuka; Gábor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

Noise-shaping techniques applied to switched-capacitor voltage regulators. - Arun Rao; William McIntyre; Un-Ku Moon; Gábor C. Temes (IEEE J. Solid State Circuits, 2005)

Design-oriented estimation of thermal noise in switched-capacitor circuits. - Richard Schreier; José B. Silva; Jesper Steensgaard; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 0.6V Highly Linear Switched-R-MOSFET-C Filter. - Peter Kurahashi; Pavan Kumar Hanumolu; Gabor C. Temes; Un-Ku Moon (CICC, 2006)

Incremental Delta-Sigma Structures for DC Measurement: an Overview. - János Márkus; Philippe Deval; Vincent Quiquempoix; José B. Silva; Gabor C. Temes (CICC, 2006)

Enhanced split-architecture delta-sigma ADC. - Kyehyung Lee; Gabor C. Temes (ICECS, 2006)

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections. - Hirokazu Yoshizawa; Gabor C. Temes (ISCAS, 2006)

A low-power 22-bit incremental ADC. - Vincent Quiquempoix; Philippe Deval; Alexandre Barreto; Gabriele Bellini; János Márkus; José B. Silva; Gabor C. Temes (IEEE J. Solid State Circuits, 2006)

A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. - Xuefeng Chen; Yan Wang; Yoshihisa Fujimoto; Pascal Lo Ré; Yusuke Kanazawa; Jesper Steensgaard; Gabor C. Temes (CICC, 2007)

Noise-Coupled Multi-Cell Delta-Sigma ADCs. - Kyehyung Lee; Gabor C. Temes; Franco Maloberti (ISCAS, 2007)

Mixed-Order Sturdy MASH Delta-Sigma Modulator. - Nima Maghari; Sunwoo Kwon; Gabor C. Temes; Un-Ku Moon (ISCAS, 2007)

Predictive Switched-Capacitor Track-and-Hold Amplifier with Improved Linearity. - Hirokazu Yoshizawa; Gabor C. Temes (ISCAS, 2007)

A Segmented Data-Weighted-Averaging Technique. - Zhenyong Zhang; Gabor C. Temes (ISCAS, 2007)

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters. - Peter Kurahashi; Pavan Kumar Hanumolu; Gabor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2007)

Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections. - Hirokazu Yoshizawa; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

New architectures for low-power delta-sigma analog-to-digital converter. - Gabor C. Temes (APCCAS, 2008)

A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers. - Yan Wang; Kyehyung Lee; Gabor C. Temes (CICC, 2008)

Efficient fully-floating double-sampling integrator for DeltaSigma ADCs. - Kyehyung Lee; Jeongseok Chae; Gabor C. Temes (ISCAS, 2008)

A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (ISSCC, 2008)

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. - Min-Gyu Kim; Gil-Cho Ahn; Pavan Kumar Hanumolu; Sanghyeon Lee; Sang-Ho Kim; Seung-Bin You; Jae-Whui Kim; Gabor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (IEEE J. Solid State Circuits, 2008)

Noise-Power Optimization of Incremental Data Converters. - Jesper Steensgaard; Zhiqing Zhang; Wenhuan Yu; Attila Sárhegyi; Luca Lucchese; Dae-Ik Kim; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Improved Low-distortion DeltaSigma ADC Topology. - Kyehyung Lee; Gabor C. Temes (ISCAS, 2009)

An Enhanced Dual-path DeltaSigma Analog-to-digital Converter. - Yoshio Nishida; Gabor C. Temes (ISCAS, 2009)

A Digital Calibration Technique for DAC Mismatches in Delta-sigma Modulators. - Wenhuan Yu; Gabor C. Temes (ISCAS, 2009)

Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder. - Yan Wang; Gabor C. Temes (SoCC, 2009)

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver. - Kyehyung Lee; Qingdong Meng; Tetsuro Sugimoto; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Un-Ku Moon; Gabor C. Temes (IEEE J. Solid State Circuits, 2009)

An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD. - Kyehyung Lee; Matthew R. Miller; Gabor C. Temes (IEEE J. Solid State Circuits, 2009)

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. - Jeongseok Chae; Sanghyeon Lee; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2010)

82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction. - Wenhuan Yu; Mehmet Aslan; Gabor C. Temes (CICC, 2010)

Radix-based digital correction technique for two-capacitor DACs. - Jinzhou Cao; Gabor C. Temes (ISCAS, 2010)

Energy-efficient time-interleaved and pipelined SAR ADCs. - Jiaming Lin; Wenhuan Yu; Gabor C. Temes (ISCAS, 2010)

Noise-coupled low-power incremental ADCs. - Yan Wang; Chia-Hung Chen; Wenhuan Yu; Gabor C. Temes (ISCAS, 2010)

Design techniques for discrete-time delta-sigma ADCs with extra loop delay. - Yan Wang; Gabor C. Temes (ISCAS, 2010)

Switched-resistor tuning technique for highly linear Gm-C filter design. - Tao Wang; Gabor C. Temes (ISCAS, 2010)

Two-step junction-splitting SAR analog-to-digital converter. - Wenhuan Yu; Jiaming Lin; Gabor C. Temes (ISCAS, 2010)

A new zero-optimization scheme for noise-coupled ΔΣ ADCs. - Ramin Zanbaghi; Terri S. Fiez; Gabor C. Temes (ISCAS, 2010)

An Enhanced Dual-Path DeltaSigma A/D Converter. - Yoshio Nishida; Koichi Hamashita; Gabor C. Temes (IEICE Trans. Electron., 2010)

Correction to "An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and - 98 dB THD" [Aug 09 2202-2211]. - Kyehyung Lee; Matthew R. Miller; Gabor C. Temes (IEEE J. Solid State Circuits, 2010)

Micropower Data Converters: A Tutorial. - Gabor C. Temes (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. - Sanghyeon Lee; Jeongseok Chae; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2011)

A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. - Ramin Zanbaghi; Saurabh Saxena; Gabor C. Temes; Terri S. Fiez (CICC, 2011)

Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay. - Yan Wang; Pavan Kumar Hanumolu; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Multi-channel mixed-signal noise source with applications to stochastic equalization. - Jinzhou Cao; Raviv Raich; Gabor C. Temes; Gert Cauwenberghs (ISCAS, 2012)

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits. - Chia-Hung Chen; Joseph Crop; Jeongseok Chae; Patrick Chiang 001; Gabor C. Temes (ISCAS, 2012)

Digital foreground calibration methods for SAR ADCs. - Wei Li; Tao Wang; Gabor C. Temes (ISCAS, 2012)

Calibration technique for SAR analog-to-digital converters. - Tao Tong; Wenhuan Yu; Pavan Kumar Hanumolu; Gabor C. Temes (ISCAS, 2012)

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. - Ramin Zanbaghi; Saurabh Saxena; Gabor C. Temes; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

The Old Professor in Action. - Gabor C. Temes; Laszlo Solymar (Proc. IEEE, 2013)

A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Xin Meng; Nancy Qian; Ed Liu; Phillip Elliott; Gabor C. Temes (A-SSCC, 2014)

A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Patrick Yin Chiang; Gabor C. Temes (CICC, 2014)

A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration. - Wei Li; Tao Wang; Jorge A. Grilo; Gabor C. Temes (CICC, 2014)

A fully-differential input amplifier with band-pass filter for biosensors. - Xin Meng; Wei Li; Gabor C. Temes (ISCAS, 2014)

A low-power parasitic-insensitive switched-capacitor integrator for Delta-Sigma ADCs. - Xin Meng; Tao Wang; Gabor C. Temes (ISCAS, 2014)

A continuous-time ΔΣ modulator with a digital technique for excess loop delay compensation. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Xin Meng; Gabor C. Temes (ISCAS, 2014)

A noise-coupled low-distortion delta-sigma ADC with shifted loop delays. - Xin Meng; Yi Zhang 023; Tao He 001; Gabor C. Temes (MWSCAS, 2014)

Double-sampled wideband delta-sigma ADCs with shifted loop delays. - Xin Meng; Tao He 001; Yi Zhang 023; Gabor C. Temes (MWSCAS, 2014)

Bootstrapping techniques for floating switches in switched-capacitor circuits. - Xin Meng; Gabor C. Temes (MWSCAS, 2014)

Low-power duty-cycle tuned filters. - Xin Meng; Gabor C. Temes (MWSCAS, 2014)

Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems. - Pedram Payandehnia; Hamidreza Maghami; Xin Meng; Gabor C. Temes; Hirokazu Yoshizawa (MWSCAS, 2014)

Multi-step counting ADC. - Pedram Payandehnia; Xin Meng; Gabor C. Temes (MWSCAS, 2014)

A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performance. - Vahid Behravan; Shuo Li; Neil E. Glover; Chia-Hung Chen; Mohammed Shoaib; Gabor C. Temes; Patrick Yin Chiang (CICC, 2015)

A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. - Xin Meng; Jinzhou Cao; Tao He 001; Yi Zhang 023; Gabor C. Temes; Mitsuru Aniya; Kazuki Sobue; Koichi Hamashita (ESSCIRC, 2015)

A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface. - Tao He 001; Yi Zhang 023; Xin Meng; Gabor C. Temes; Chia-Hung Chen (ISCAS, 2015)

A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays. - Xin Meng; Yi Zhang 023; Tao He 001; Pedram Payandehnia; Gabor C. Temes (ISCAS, 2015)

A passive CMOS low-pass filter for high speed and high SNDR applications. - Pedram Payandehnia; Ali Fazli Yeknami; Xin Meng; Chao Yang; Gabor C. Temes (ISCAS, 2015)

Two-stage ΔΣ ADC with noise-coupled VCO-based quantizer. - Mahmoud Sadollahi; Gabor C. Temes (ISCAS, 2015)

Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces. - Chia-Hung Chen; Tao He 001; Yi Zhang 023; Gabor C. Temes (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

A Micro-Power Two-Step Incremental Analog-to-Digital Converter. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Patrick Yin Chiang; Gabor C. Temes (IEEE J. Solid State Circuits, 2015)

In Defense of Engineering Education [Point of View]. - Gabor C. Temes; Laszlo Solymar (Proc. IEEE, 2015)

Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays. - Xin Meng; Yi Zhang 023; Tao He 001; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

History, present state-of-art and future of incremental ADCs. - Chia-Hung Chen; Yi Zhang 023; Gabor C. Temes (ESSCIRC, 2016)

Power-on digital calibration method for delta-Sigma ADCs. - Jinzhou Cao; Xin Meng; Gabor C. Temes; Wenhuan Yu (ISCAS, 2016)

An incremental analog-to-digital converter with multi-step extended counting for sensor interfaces. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Gabor C. Temes (ISCAS, 2016)

A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Gabor C. Temes (VLSI Circuits, 2016)

A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Kazuki Sobue; Koichi Hamashita; Gabor C. Temes (CICC, 2017)

Incremental ADC with parallel counting. - Tao He 001; Chia-Hung Chen; Yi Zhang 023; Gabor C. Temes (MWSCAS, 2017)

Pseudo-pseudo-differential circuits. - Tao He 001; Manjunath Kareppagoudr; Un-Ku Moon; Gabor C. Temes; Yi Zhang 023 (MWSCAS, 2017)

An 11-bit 250-nW 10-kS/s SAR ADC with doubled input range for biomedical applications. - Mahmoud Sadollahi; Gabor C. Temes (MWSCAS, 2017)

Passive 3rd order delta-sigma ADC with VCO-based quantizer. - Mahmoud Sadollahi; Gabor C. Temes (MWSCAS, 2017)

A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Gabor C. Temes (IEEE J. Solid State Circuits, 2017)

System-level noise filtering and linearization. - Tao He 001; Gabor C. Temes (CICC, 2018)

A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. - Tao He 001; Michael Ashburn; Stacy Ho; Yi Zhang 023; Gabor C. Temes (ISSCC, 2018)

Single-Loop Delta-Sigma ADC Using Noise-Coupled VCO Quantizer. - Mahmoud Sadollahi; Lukang Shi; Yanchao Wang 001; Gabor C. Temes (MWSCAS, 2018)

A 13b-ENOB Noise Shaping SAR ADC with a Two-Capacitor DAC. - Lukang Shi; Yi Zhang 023; Yanchao Wang 001; Manjunath Kareppagoudr; Mahmoud Sadollahi; Gabor C. Temes (MWSCAS, 2018)

Robust Continuous-Time MASH Delta Sigma Modulator. - Yanchao Wang 001; Lukang Shi; Tao He 001; Yi Zhang 023; Chia-Hung Chen; Gabor C. Temes (MWSCAS, 2018)

The Twin Arts of Writing and Revising Technical Articles. - Gabor C. Temes; Laszlo Solymar (Proc. IEEE, 2018)

A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3. - Pedram Payandehnia; Hamidreza Maghami; Hossein Mirzaie; Manjunath Kareppagoudr; Siladitya Dey 002; Massoud Tohidian; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications. - Mahmoud Sadollahi; Koichi Hamashita; Kazuki Sobue; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Amplifier-Free 0-2 SAR-VCO MASH ΔΣ ADC. - Pedram Payandehnia; Hamidreza Maghami; Hossein Mirzaie; Matthew L. Johnston; Gabor C. Temes (ISCAS, 2019)

Predictive Noise Shaping SAR ADC. - Jyotindra R. Shakya; Ajmal K. Vadakkan; Gabor C. Temes (ISCAS, 2019)

Passive slew rate enhancement technique for Switched-Capacitor Circuits. - Manjunath Kareppagoudr; Emanuel Caceres; Yu-Wen Kuo; Jyotindra R. Shakya; Yanchao Wang 001; Gabor C. Temes (MWSCAS, 2019)

Thoughts on Engineering Creativity [Point of View]. - Gabor C. Temes (Proc. IEEE, 2019)

Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits. - Tao He 001; Manjunath Kareppagoudr; Yi Zhang 023; Emanuel Caceres; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 10-MHz BW 77.9 dB SNDR DT MASH Δ!Σ ADC With NC-VCO-Based Quantizer and OPAMP Sharing. - Mahmoud Sadollahi; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial. - Pedram Payandehnia; Tao He 001; Yanchao Wang 001; Gabor C. Temes (CICC, 2020)

Pseudo-Pseudo-Differential Multibit Delta-Sigma Modulator. - Emanuel Caceres; Manjunath Kareppagoudr; Jyotindra R. Shakya; Gabor C. Temes (MWSCAS, 2020)

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR. - Lukang Shi; Eashwar Thaigarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (MWSCAS, 2020)

Slewing Mitigation Technique for Switched Capacitor Circuits. - Manjunath Kareppagoudr; Jyotindra R. Shakya; Emanuel Caceres; Yu-Wen Kuo; Gabor C. Temes (IEEE Trans. Circuits Syst., 2020)

Efficient Calibration of Feedback DAC in Delta Sigma Modulators. - Jyotindra R. Shakya; Gabor C. Temes (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Incremental Delta-Sigma ADCs: A Tutorial Review. - Zhichao Tan; Chia-Hung Chen; Youngcheol Chae; Gabor C. Temes (IEEE Trans. Circuits Syst., 2020)

A Charge-Domain Switched-Gm-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique. - Yang Xu 005; Praveen Kumar Venkatachala; Yue Hu; Spencer Leuenberger; Gabor C. Temes; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. - Yanchao Wang 001; Siladitya Dey 002; Tao He 001; Lukang Shi; Jiawei Zheng; Manjunath Kareppagoudr; Yi Zhang 023; Kazuki Sobue; Koichi Hamashita; Koji Tomioka; Gabor C. Temes (A-SSCC, 2021)

Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion. - Manjunath Kareppagoudr; Emanuel Caceres; Gabor C. Temes (MWSCAS, 2021)

Low-Distortion Correlated Level Shifting Sample-and-Hold Stage. - Alexander Pierce; Eashwar Thaigarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (NEWCAS, 2021)

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR. - Lukang Shi; Eashwar Thiagarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Switched-Capacitor Circuits. - David J. Allstot; Un-Ku Moon; Gabor C. Temes (CICC, 2022)

A Second-Order Passive Noise-Shaping SAR ADC With 4× Passive Gain and A Two-Input-Pair Comparator. - Hanyu Wang; Gabor C. Temes (ISCAS, 2022)

A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC. - Manxin Li; Calvin Yoji Lee; Hanyu Wang; Gabor C. Temes; Un-Ku Moon (ISCAS, 2023)

Mismatch Shaping for Binary-Coded DAC. - Jyotindra R. Shakya; Gabor C. Temes (ISCAS, 2023)

A Low-Distortion Power-Efficient Feedforward Technique for DT Delta-Sigma ADCs. - Hanyu Wang; Gabor C. Temes (ISCAS, 2023)

Reciprocity and Inter-Reciprocity: A Tutorial - Part I: Linear Time-Invariant Networks. - Shanthi Pavan; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Reciprocity and Inter-Reciprocity: A Tutorial - Part II: Linear Periodically Time-Varying Networks. - Shanthi Pavan; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Multi-Residue Two-Step Incremental ADC. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (MWSCAS, 2024)

Wideband Low-Distortion Noise-Coupled Delta-Sigma ADC. - Hanyu Wang; Faraz Adin; Un-Ku Moon; Gabor C. Temes (MWSCAS, 2024)

A 16 GΩ Input Impedance Amplifier with Flicker Noise Reduction for Neural Recording Applications. - Jyotindra R. Shakya; Gabor C. Temes; Faraz Adin (CICC, 2025)

An 89.5 dB SNDR 500 kHz BW Largely Passive Fourth-Order Noise-Coupled Delta-Sigma Modulator. - Hanyu Wang; Faraz Adin; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

98-dB SNDR Multi-Residue Two-Step Incremental ADC With Two-Capacitor SAR. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (IEEE Trans. Circuits Syst. II Express Briefs, 2025)