Cost Effective 2×2 Inner Product Processors. - Béla Fehér; Gábor Szedö (FPL, 1998)

Reconfigurable target recognition system (poster abstract). - Gábor Szedö; Sandeep Neema; Jason Scott; Ted Bapty (FPGA, 2000)

High-Performance Timing-Driven Rank Filter. - Péter Szántó; Gábor Szedö; Béla Fehér (VLSI Design, 2008)