Implementation comparisons of the QR decomposition for MIMO detection. - Gabriel Luca Nazar; Christina Gimmler; Norbert Wehn (SBCCI, 2010)

An Area Effective Parity-Based Fault Detection Technique for FPGAs. - Gabriel L. Nazar; Luigi Carro (DFT, 2011)

Energy efficient pseudo-cache architecture through fine-grained reconfigurability. - Gabriel L. Nazar; Luigi Carro (ISCAS, 2011)

Fast single-FPGA fault injection platform. - Gabriel L. Nazar; Luigi Carro (DFT, 2012)

Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors. - Fábio P. Itturriet; Ronaldo Rodrigues Ferreira; Gustavo Girão; Gabriel L. Nazar; Álvaro F. Moreira; Luigi Carro (DSD, 2012)

Fast error detection through efficient use of hardwired resources in FPGAs. - Gabriel L. Nazar; Luigi Carro (ETS, 2012)

Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs. - Gabriel L. Nazar; Luigi Carro (FCCM, 2012)

Adapting communication for adaptable processors: A multi-axis reconfiguration approach. - Paulo C. Santos 001; Gabriel L. Nazar; Luigi Carro; Fakhar Anjam; Stephan Wong (ReConFig, 2012)

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor. - Fakhar Anjam; Stephan Wong; Luigi Carro; Gabriel L. Nazar; Mateus B. Rutzig (ICSAMOS, 2012)

Scrubbing unit repositioning for fast error repair in FPGAs. - Gabriel L. Nazar; Leonardo P. Santos; Luigi Carro (CASES, 2013)

Accelerated FPGA repair through shifted scrubbing. - Gabriel L. Nazar; Leonardo P. Santos; Luigi Carro (FPL, 2013)

Reliable execution of statechart-generated correct embedded software under soft errors. - Ronaldo Rodrigues Ferreira; Thomas Klotz; Thilo Vörtler; Jean da Rolt; Gabriel L. Nazar; Álvaro Freitas Moreira; Luigi Carro; Karsten Einwich (DDECS, 2014)

Adaptive Low-Power Architecture for High-Performance and Reliable Embedded Computing. - Ronaldo Rodrigues Ferreira; Jean da Rolt; Gabriel L. Nazar; Álvaro Freitas Moreira; Luigi Carro (DSN, 2014)

Reducing embedded software radiation-induced failures through cache memories. - Thiago Santini; Paolo Rech; Gabriel L. Nazar; Luigi Carro; Flávio Rech Wagner (ETS, 2014)

Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity. - Giovanni Bruni; Paolo Rech; Lucas A. Tambara; Gabriel L. Nazar; Fernanda Gusmão de Lima Kastensmidt; Ricardo Reis 001; Alessandro Paccagnella (VLSI-SoC, 2014)

Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems. - Fábio P. Itturriet; Gabriel L. Nazar; Ronaldo Rodrigues Ferreira; Álvaro Freitas Moreira; Luigi Carro (ACM Trans. Reconfigurable Technol. Syst., 2014)

Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture. - Ronaldo Rodrigues Ferreira; Ernesto Sánchez 001; Jean da Rolt; Gabriel L. Nazar; Álvaro F. Moreira; Luigi Carro; Matteo Sonza Reorda (LATS, 2015)

Improving FPGA repair under real-time constraints. - Gabriel L. Nazar (Microelectron. Reliab., 2015)

Fine-Grained Fast Field-Programmable Gate Array Scrubbing. - Gabriel Luca Nazar; Leonardo Pereira Santos; Luigi Carro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low Cost Dynamic Scrubbing for Real-Time Systems. - Leonardo P. Santos; Gabriel L. Nazar; Luigi Carro (ARC, 2016)

Low cost resilient regular expression matching on FPGAs. - Marcos T. Leipnitz; Eduardo Nunes de Souza; Gabriel L. Nazar (DFT, 2016)

Scalable memory architecture for soft-core processors. - Tiago T. Jost; Gabriel L. Nazar; Luigi Carro (ICCD, 2016)

A fault injection platform for FPGA-based communication systems. - Marcos T. Leipnitz; L. H. Geferson; Gabriel L. Nazar (LASCAS, 2016)

Improving performance in VLIW soft-core processors through software-controlled scratchpads. - Tiago T. Jost; Gabriel L. Nazar; Luigi Carro (SAMOS, 2016)

Searching with a Corrupted Heuristic. - Levi H. S. Lelis; Richard Anthony Valenzano; Gabriel L. Nazar; Roni Stern (SOCS, 2016)

SBESC 2015 guest editors' introduction. - Gabriel L. Nazar (Des. Autom. Embed. Syst., 2016)

Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication. - Ronaldo Rodrigues Ferreira; Gabriel L. Nazar; Jean da Rolt; Álvaro F. Moreira; Luigi Carro (ACM Trans. Embed. Comput. Syst., 2016)

Beyond Cross-Section: Spatio-Temporal Reliability Analysis. - Thiago Santini; Paolo Rech; Gabriel Luca Nazar; Flávio Rech Wagner (ACM Trans. Embed. Comput. Syst., 2016)

An energy-efficient memory hierarchy for multi-issue processors. - Tiago T. Jost; Gabriel L. Nazar; Luigi Carro (DATE, 2017)

Exploring redundancy granularities to repair real-time FPGA-based systems. - Leonardo Pereira Santos; Gabriel L. Nazar; Luigi Carro (Microprocess. Microsystems, 2017)

Precise evaluation of the fault sensitivity of OoO superscalar processors. - Rafael Billig Tonetto; Gabriel L. Nazar; Antonio Carlos Schneider Beck (DATE, 2018)

Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching. - Marcos T. Leipnitz; Gabriel L. Nazar (J. Electron. Test., 2018)

Repair of FPGA-Based Real-Time Systems With Variable Slacks. - Leonardo Pereira Santos; Gabriel Luca Nazar; Luigi Carro (ACM Trans. Design Autom. Electr. Syst., 2018)

High-Level Synthesis of Resource-oriented Approximate Designs for FPGAs. - Marcos T. Leipnitz; Gabriel L. Nazar (DAC, 2019)

Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors. - Douglas Maciel Cardoso; Rafael Billig Tonetto; Marcelo Brandalero; Luciano Agostini; Gabriel L. Nazar; José Rodrigo Azambuja; Antonio Carlos Schneider Beck (ICECS, 2019)

Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation. - Wagner Penny; Jones Goebel; Douglas Corrêa; Anderson Martins; Gabriel L. Nazar; Luciano Agostini; Daniel Palomino 001; Marcelo Schiavon Porto; Bruno Zatt (ICECS, 2019)

Cost-effective Resilient FPGA-based LDPC Decoder Architecture. - Eduardo Nunes de Souza; Gabriel L. Nazar (IOLTS, 2019)

A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors. - Rafael Billig Tonetto; Douglas Maciel Cardoso; Marcelo Brandalero; Luciano Agostini; Gabriel L. Nazar; José Rodrigo Azambuja; Antonio Carlos Schneider Beck (VLSI-SoC, 2019)

High-Level Synthesis of Approximate Designs under Real-Time Constraints. - Marcos T. Leipnitz; Gabriel L. Nazar (ACM Trans. Embed. Comput. Syst., 2019)

High-level synthesis of throughput-optimized and energy-efficient approximate designs. - Marcos T. Leipnitz; Gabriel L. Nazar (CF, 2020)

A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores. - Rafael Billig Tonetto; Hiago Mayk G. de A. Rocha; Gabriel L. Nazar; Antonio Carlos Schneider Beck (DAC, 2020)

Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis. - Marcos T. Leipnitz; Gabriel L. Nazar (ICCD, 2020)

Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC. - Wagner Penny; Guilherme Corrêa 001; Luciano Agostini; Daniel Palomino 001; Marcelo Schiavon Porto; Gabriel L. Nazar; Bruno Zatt (ISCAS, 2020)

A Reliability-Oriented Machine Learning Strategy for Heterogeneous Multicore Application Mapping. - Rafael Billig Tonetto; Hiago Mayk G. de A. Rocha; Bruno Zatt; Antonio Carlos Schneider Beck; Gabriel L. Nazar (ISCAS, 2020)

ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs. - Ricardo Coelho; Felipe Tanus; Álvaro F. Moreira; Gabriel L. Nazar (ISVLSI, 2020)

Enhancing Real-Time Motion Estimation through Approximate High-Level Synthesis. - Marcos T. Leipnitz; Murilo R. Perleberg; Marcelo Schiavon Porto; Gabriel L. Nazar (ISVLSI, 2020)

Firefly: An Open-source Rocket-based Intermittent Framework. - Hiago Rocha; Guilherme Korol; Michael G. Jordan; Arthur M. Krause; Ronaldo Silveira; Caio Vieira; Philippe O. A. Navaux; Gabriel L. Nazar; Luigi Carro; Antonio Carlos Schneider Beck (SBCCI, 2020)

A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions. - Gabriel S. Niemiec; Luis M. S. Batista; Alberto E. Schaeffer-Filho; Gabriel L. Nazar (IEEE Commun. Surv. Tutorials, 2020)

SoMMA: A software-managed memory architecture for multi-issue processors. - Tiago Trevisan Jost; Gabriel Luca Nazar; Luigi Carro (Microprocess. Microsystems, 2020)

VNFAccel: An FPGA-based Platform for Modular VNF Components Acceleration. - Filipe Bachini Lopes; Gabriel Luca Nazar; Alberto E. Schaeffer-Filho (IM, 2021)

Lightweight Dual Modular Redundancy through Approximate Computing. - Gabriel L. Nazar; Pedro H. Kopper; Marcos T. Leipnitz; Ben H. H. Juurlink (SBESC, 2021)

SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing. - Rafael Billig Tonetto; Antonio Carlos Schneider Beck; Gabriel L. Nazar (DSD, 2022)

Desafios para a Computação Energeticamente Eficiente. - Luigi Carro; Gabriel Luca Nazar (Escola de Computação PPGC/UFRGS 50 Anos, 2023)

GRASP-based High-Level Synthesis Design Space Exploration for FPGAs. - Níkolas P. Schuster; Gabriel L. Nazar (SBESC, 2023)

Modular VNF Components Acceleration With FPGA Overlays. - Filipe Bachini Lopes; Alberto E. Schaeffer-Filho; Gabriel Luca Nazar (IEEE Trans. Netw. Serv. Manag., 2023)

Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs. - Marcos T. Leipnitz; Gabriel L. Nazar (ACM Trans. Reconfigurable Technol. Syst., 2023)

FPGAs for Network Function Virtualization: Challenges in Placement and Partitioning. - Victor Sberse Guerra; Gabriel Luca Nazar (SBCCI, 2024)

A variation-aware methodology for improved processor designs for the edge computing domain. - Rafael Billig Tonetto; Gabriel L. Nazar; Antonio Carlos Schneider Beck (Des. Autom. Embed. Syst., 2025)