Gabriel Rodríguez

Orcid: 0000-0002-0338-3655

Affiliations:
  • University of A Coruña, Spain


According to our database1, Gabriel Rodríguez authored at least 40 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Formal Verification of Source-to-Source Transformations for HLS.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2022
MARTA: Multi-configuration Assembly pRofiler and Toolkit for performance Analysis.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Custom High-Performance Vector Code Generation for Data-Specific Sparse Computations.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings.
IEEE Access, 2021

PolyBench/Python: benchmarking Python environments with polyhedral optimizations.
Proceedings of the CC '21: 30th ACM SIGPLAN International Conference on Compiler Construction, 2021

2020
Coherence Traffic in Manycore Processors with Opaque Distributed Directories.
CoRR, 2020

2019
Affine Modeling of Program Traces.
IEEE Trans. Computers, 2019

Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors.
IEEE Access, 2019

Simulating the Network Activity of Modern Manycores.
IEEE Access, 2019

Generating piecewise-regular code from irregular structures.
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

Effect of Distributed Directories in Mesh Interconnects.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Architectural exploration of heterogeneous memory systems.
CoRR, 2018

2016
Locality-Aware Automatic Parallelization for GPGPU with OpenHMPP Directives.
Int. J. Parallel Program., 2016

An Application-Level Solution for the Dynamic Reconfiguration of MPI Applications.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016

Portable Application-level Checkpointing for Hybrid MPI-OpenMP Applications.
Proceedings of the International Conference on Computational Science 2016, 2016

Trace-based affine reconstruction of codes.
Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

2015
I/O Optimization in the Checkpointing of OpenMP Parallel Applications.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

2014
In-memory application-level checkpoint-based migration for MPI programs.
J. Supercomput., 2014

Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy.
ACM Trans. Archit. Code Optim., 2014

Extending an Application-Level Checkpointing Tool to Provide Fault Tolerance Support to OpenMP Applications.
J. Univers. Comput. Sci., 2014

Failure Avoidance in MPI Applications Using an Application-Level Approach.
Comput. J., 2014

A parallelizing compiler for multicore systems.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

2013
A novel compiler support for automatic parallelization on multicore systems.
Parallel Comput., 2013

Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint Sizes.
New Gener. Comput., 2013

Compiler-Assisted Checkpointing of Parallel Codes: The Cetus and LLVM Experience.
Int. J. Parallel Program., 2013

Building resilient cloud services using DDDAS and moving target defence.
Int. J. Cloud Comput., 2013

Resilient Dynamic Data Driven Application Systems (rDDDAS).
Proceedings of the International Conference on Computational Science, 2013

Achieving Checkpointing Global Consistency Through a Hybrid Compile Time and Runtime Protocol.
Proceedings of the International Conference on Computational Science, 2013

2012
Reducing Application-level Checkpoint File Sizes: Towards Scalable Fault Tolerance Solutions.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

2011
Parallel hierarchical radiosity on hybrid platforms.
J. Supercomput., 2011

Analysis of Performance-impacting Factors on Checkpointing Frameworks: The CPPC Case Study.
Comput. J., 2011

An Application Level Approach for Proactive Process Migration in MPI Applications.
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011

2010
Performance evaluation of an application-level checkpointing solution on grids.
Future Gener. Comput. Syst., 2010

CPPC: a compiler-assisted tool for portable checkpointing of message-passing applications.
Concurr. Comput. Pract. Exp., 2010

Achieving Fault Tolerance on Grids with the CPPC Framework and the GridWay Metascheduler.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

2009
A Heuristic Approach for the Automatic Insertion of Checkpoints in Message-Passing Codes.
J. Univers. Comput. Sci., 2009

2008
A Fault Tolerance Solution for Sequential and MPI Applications on the Grid.
Scalable Comput. Pract. Exp., 2008

2007
CPPC-G: Fault-Tolerant Applications on the Grid.
Proceedings of the Parallel Processing and Applied Mathematics, 2007

Enhancing Fault-Tolerance of Large-Scale MPI Scientific Applications.
Proceedings of the Parallel Computing Technologies, 2007

2006
Controller/Precompiler for Portable Checkpointing.
IEICE Trans. Inf. Syst., 2006


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