Complexity in an Industrial flyback converter. - Salvatore Baglio; Luigi Fortuna; Gabriele Manganaro; Rosario Cristaudo (J. Circuits Syst. Comput., 1995)

Generation of n-double scrolls via cellular neural networks. - Paolo Arena; Salvatore Baglio; Luigi Fortuna; Gabriele Manganaro (Int. J. Circuit Theory Appl., 1996)

DNA computing based on chaos. - Gabriele Manganaro; José Pineda de Gyvez (ICEC, 1997)

Cellular neural networks to explore complexity. - Paolo Arena; Riccardo Caponetto; Luigi Fortuna; Gabriele Manganaro (Soft Comput., 1997)

A triple 8b, 80MSPS 3.3 V graphics digitizer. - Irfan A. Chaudrhry; Sung-Ung Kwak; Gabriele Manganaro; Maher Sarraj; T. Lakshmi Viswanathan (ISCAS, 2000)

Nonlinear Computability Based on Chaos. - Gabriele Manganaro; José Pineda de Gyvez (Int. J. Bifurc. Chaos, 2000)

An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits. - Gabriele Manganaro (ICECS, 2001)

A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer. - Gabriele Manganaro; Sung-Ung Kwak; Alex R. Bugeja (CICC, 2003)

A behavioral modeling approach to the design of a low jitter clock source. - Gabriele Manganaro; Sung-Ung Kwak; SeongHwan Cho; Anurag Pulincherry (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer. - Gabriele Manganaro; Sung-Ung Kwak; Alex R. Bugeja (IEEE J. Solid State Circuits, 2004)

A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration. - J. Li; Robert Leboeuf; Matthew Courcy; Gabriele Manganaro (CICC, 2007)

Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW. - Ivano Galdi; Edoardo Bonizzoni; Franco Maloberti; Gabriele Manganaro; Piero Malcovati (ESSCIRC, 2007)

A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC. - Byung Geun Lee; Byung-Moo Min; Gabriele Manganaro; Jonathan W. Valvano (ISSCC, 2008)

40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW. - Ivano Galdi; Edoardo Bonizzoni; Piero Malcovati; Gabriele Manganaro; Franco Maloberti (IEEE J. Solid State Circuits, 2008)

A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC. - Byung Geun Lee; Byung-Moo Min; Gabriele Manganaro; Jonathan W. Valvano (IEEE J. Solid State Circuits, 2008)

Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference. - Andrew Marshall; Sakir Sezer; Gabriele Manganaro (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits Conference. - Shahriar Mirabbasi; John W. M. Rogers; Gabriele Manganaro (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Advanced transmitters for wireless infrastructure. - Gabriele Manganaro; Domine Leenaerts; Francesco Dantoni; Andrea Baschirotto; Robert Bogdan Staszewski; Nikolaus Klemmer; Seongchol Hong (ISSCC, 2011)

Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010). - Mohab Anis; Howard C. Luong; Gabriele Manganaro (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Guest Editorial Special Issue on ISCAS 2010. - Maged Ghoneima; Yong Lian 001; Gabriele Manganaro; Shahriar Mirabbasi; Christian Piguet; Wouter A. Serdijn (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. - Hyungil Chae; Jaehun Jeong; Gabriele Manganaro; Michael P. Flynn (ISSCC, 2012)

Guest Editorial Special Issue on ISCAS 2011. - Tor Sverre Lande; Peter T. J. Liang; Gabriele Manganaro; Eduardo A. B. da Silva; Aleksandar Tasic (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Incoming Editorial. - Gabriele Manganaro (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Progress update and a look ahead. - Gabriele Manganaro (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Outgoing Editorial. - Gabriele Manganaro (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. - Hyungil Chae; Jaehun Jeong; Gabriele Manganaro; Michael P. Flynn (IEEE J. Solid State Circuits, 2014)

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; Nevena Rakuljic; et al. (IEEE J. Solid State Circuits, 2017)

Emerging data converter architectures and techniques. - Gabriele Manganaro (CICC, 2018)

In-situ nonlinear calibration of a RF signal chain. - Nevena Rakuljic; Carroll Speir; Eric Otte; Jeff Bray; Corey Petersen; Gabriele Manganaro (ISCAS, 2018)

Inaugural Issue of the IEEE Open Journal of Circuits and Systems: Welcome Note. - Gabriele Manganaro (IEEE Open J. Circuits Syst., 2020)

New Year Editorial. - Gabriele Manganaro (IEEE Open J. Circuits Syst., 2021)

Editorial on the Special Section on the 2021 IEEE International Symposium on Integrated Circuits and Systems. - Gabriele Manganaro (IEEE Open J. Circuits Syst., 2021)

A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET. - Athanasios Ramkaj; Adalberto Cantoni; Gabriele Manganaro; Siddharth Devarajan; Michiel Steyaert; Filip Tavernier (VLSI Technology and Circuits, 2022)

Editorial: Where Are We Now and Where Do We Go From Here. - Gabriele Manganaro (IEEE Open J. Circuits Syst., 2022)

A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm. - Wei-Hsin Tseng; Willy Lin; Chung-Wei Hsu; Chang-Yang Huang; Yu-Sian Lin; Hung-Yi Huang; HsinWei Chen; Sheng-Hui Liao; Kuan-Dar Chen; Jon Strange; Gabriele Manganaro (ISSCC, 2023)

New Year Editorial 2023. - Gabriele Manganaro; Nicole McFarlane (IEEE Open J. Circuits Syst., 2023)

Generalized Sampling-Based Multi-Channel Sampling of Signals Realized With Pure Delay Analog Filters and Digital FIR Reconstruction Filters. - Bibhudatta Sahoo 002; Gabriele Manganaro (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. - Juzheng Liu; Ayman Shabra; Stacy Ho; Gabriele Manganaro; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. - Rishabh Mittal; Hajime Shibata; Sharvil Patil; Erik Krommenhoek; Prawal Shrestha; Gabriele Manganaro; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2024)

24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC. - Cheng-En Hsieh; Gabriele Manganaro; Sheng-Hui Liao; Jack Weng; Tsun-Yuan Fan; Alec Chin; Tsung-Chih Hung; Jonathan X. Wu; Chi-Lun Lo; Andy Pan; Ming-Hang Hsieh; Yun-Shiang Shu; et al. (ISSCC, 2025)