Codage des tableaux d'états des systèmes séquentiels asynchrones. - Gabrièle Saucier (1964)

Encoding of Asynchronous Sequential Networks. - Gabrièle Saucier (IEEE Trans. Electron. Comput., 1967)

Codage des automates asynchrones. - Gabrièle Saucier (1970)

State Assignment of Asynchronous Sequential Machines Using Graph Techniques. - Gabriele Saucier (IEEE Trans. Computers, 1972)

Next-State Equations of Asynchronous Sequential Machines. - Gabriele Saucier (IEEE Trans. Computers, 1972)

On balancing hardware-firmware for designing a fault-tolerant computers' series. - Bernard Courtois; Gabriele Saucier (MICRO (2), 1975)

Diversified Test Methods for Local Control Units. - Chantal Robach; Gabriele Saucier (IEEE Trans. Computers, 1975)

A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules. - M. Moalla; Gabriele Saucier; Joseph Sifakis; Marianthi Zachariades (ISCA, 1976)

Processor Testability and Design Consequences. - Chantal Robach; Gabriele Saucier; J. Lebrun (IEEE Trans. Computers, 1976)

Dynamic Testing of Control Units. - Chantal Robach; Gabriele Saucier (IEEE Trans. Computers, 1978)

Hardware description levels and test for complex circuits. - Catherine Bellon; Gabriele Saucier; José-Maria Gobbi (DAC, 1981)

Top down design and testability of VLSI circuits. - Philippe Basset; Gabriele Saucier (DAC, 1982)

Automatic generation of microprocessor test programs. - Catherine Bellon; A. Liothin; Sylvain Sadier; Gabriele Saucier; Raoul Velazco; Francois Grillot; M. Issenman (DAC, 1982)

Protection Against External Errors in a Dedicated System. - Catherine Bellon; Gabriele Saucier (IEEE Trans. Computers, 1982)

VLSI test expertise system using a control flow model. - Gabriele Saucier; Catherine Bellon (DAC, 1984)

CADOC : A System for Computer Aided Functional Test. - Catherine Bellon; Gabriele Saucier (ITC, 1984)

Design synthesis in VLSI and software engineering. - Robert Cuykendall; Antun Domic; William H. Joyner; Stephen C. Johnson; Steven H. Kelem; Dennis McBride; Jack Mostow; John E. Savage; Gabriele Saucier (J. Syst. Softw., 1984)

Systematic and optimized layout of MOS cells. - Gabriele Saucier; Ghislaine Thuau (DAC, 1985)

A Rule-Based System for the Optimal State Assignment of Controllers. - E. Dupont; Jeanne Idt; Gabriele Saucier (FJCC, 1986)

An Application of Exploratory Data Analysis Techniques to Floorplan Design. - E. F. M. Kouka; Gabriele Saucier (DAC, 1987)

ASYL: A Rule-Based System for Controller Synthesis. - Gabriele Saucier; Michel Crastes de Paulet; Pascal Sicard (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. - Manfred Glesner; M. Huch; Peter A. Ivey; T. Midwinter; Gabriele Saucier; Jacques Trilhe (GI Jahrestagung (2), 1988)

Optimized Layout of MOS Cells. - Ghislaine Thuau; Gabriele Saucier (IEEE Trans. Computers, 1988)

State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. - Gabriele Saucier; Christopher Duff; Franck Poirot (DAC, 1989)

Concurrent checking in dedicated controllers. - Régis Leveugle; Gabriele Saucier (ICCD, 1989)

A flexible architecture for neural networks. - J. Ouali; Gabriele Saucier (ICCD, 1989)

A channelless layout for multilevel synthesis with compiled cells. - Gabriele Saucier; Régis Leveugle; Pierre Abouzeid (ICCD, 1989)

Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. - Régis Leveugle; Gabriele Saucier (ITC, 1989)

Testability Expertise and Test Planning from High-Level Specifications. - Michel Crastes de Paulet; Margot Karam; Gabriele Saucier (ITC, 1989)

Multilevel Synthesis Minimizing the Routing Factor. - Pierre Abouzeid; K. Sakouti; Gabriele Saucier; Franck Poirot (DAC, 1990)

State assignment of controllers for optimal area implementation. - Gabriele Saucier; Christopher Duff; Franck Poirot (EURO-DAC, 1990)

Multi-level synthesis on PALs. - Gabriele Saucier; Pascal Sicard; Laurent Bouchet (EURO-DAC, 1990)

Design of microprocessors with built-in on-line test. - Régis Leveugle; T. Michel; Gabriele Saucier (FTCS, 1990)

Silicon compiler for neuro-ASICs. - J. Ouali; Gabriele Saucier (IJCNN, 1990)

Optimized Synthesis of Concurrently Checked Controllers. - Régis Leveugle; Gabriele Saucier (IEEE Trans. Computers, 1990)

A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. - M. Crastes; K. Sakouti; Gabriele Saucier (DAC, 1991)

A New Approach to Control Flow Checking Without Program Modification. - T. Michel; Régis Leveugle; Gabriele Saucier (FTCS, 1991)

State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. - Christopher Duff; Gabriele Saucier (ICCAD, 1991)

Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. - X. Delord; Gabriele Saucier (ITC, 1991)

Hierarchical Test Generation Based on Delayed Propagation. - Margot Karam; Régis Leveugle; Gabriele Saucier (ITC, 1991)

A Customizable Neural Processor for Distributed Neural Network. - J. Quali; Gabriele Saucier; P. Y. Alla; Jacques Trilhe; Laurent Masse-Navette (VLSI, 1991)

A reconfigurable wafer-scale memory. - Ahmed Boubekeur; Gabriele Saucier; Jacques Trilhe (IEEE J. Solid State Circuits, 1991)

Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. - T. Besson; H. Bouzouzou; M. Crastes; Ion Floricica; Gabriele Saucier (ICCD, 1992)

Logic Synthesis for Automatic Layout. - Pierre Abouzeid; Régis Leveugle; Gabriele Saucier (Synthesis for Control Dominated Circuits, 1992)

Specification and Synthesis of Communicating Finite State Machines. - H. Belhadj; Laurent Gerbaux; Marie-Claude Bertrand; Gabriele Saucier (Synthesis for Control Dominated Circuits, 1992)

Synthesis of large controllers using ROM or PLA generators. - Laurent Gerbaux; Régis Leveugle; Gabriele Saucier (Synthesis for Control Dominated Circuits, 1992)

ASYL: A Control Driven RTL Synthesis System using Library Blocks. - Anne Mignotte; Marie-Claude Bertrand; Michel Crastes de Paulet; Jérôme Rampon; Gabriele Saucier (Synthesis for Control Dominated Circuits, 1992)

Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors. - Ahmed Boubekeur; Jean-Luc Patry; Gabriele Saucier; Jacques Trilhe (Computer, 1992)

Automatic synthesis of large Moore sequencers. - Laurent Gerbaux; Gabriele Saucier (Integr., 1992)

Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. - Raphaël Rochet; Régis Leveugle; Gabriele Saucier (DFT, 1993)

A Synthesis Tool for Fault-Tolerant Finite State Machines. - Régis Leveugle; Raphaël Rochet; Gabriele Saucier; L. Martinez; C. Pitot (FTCS, 1993)

Partitioning with cone structures. - Gabriele Saucier; Daniel R. Brasen; J. P. Hiol (ICCAD, 1993)

Influence of Error Correlations on the Signature Analysis Aliasing. - Régis Leveugle; X. Delord; Gabriele Saucier (ICCD, 1993)

Design of a dedicated neural network on silicon: application to optical character recognition. - D. Jacquet; Gabriele Saucier (VLSI, 1993)

Functional versus random test generation for sequential circuits. - Margot Karam; Gabriele Saucier (J. Electron. Test., 1993)

Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. - Pierre Abouzeid; Belgacem Babba; Michel Crastes de Paulet; Gabriele Saucier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Lexicographical expressions of Boolean functions with application to multilevel synthesis. - Gabriele Saucier; Pierre Abouzeid (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Design Automation Tools for FPGA Design (Panel). - Kella Knack; Gordan Hyland; Jim Jasmin; John Frediani; Tom Reiner; Steven Trimberger; Gabriele Saucier (DAC, 1994)

Alternative Approaches to Fault Detection in FSMs. - Régis Leveugle; Raphaël Rochet; Gabriele Saucier (DFT, 1994)

FPGA Partitioning for Critical Paths. - Daniel R. Brasen; Gabriele Saucier (EDAC-ETC-EUROASIC, 1994)

Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. - T. Michel; Régis Leveugle; Gabriele Saucier; R. Doucet; P. Chapier (EDAC-ETC-EUROASIC, 1994)

Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. - C. Safinia; Régis Leveugle; Gabriele Saucier (EDAC-ETC-EUROASIC, 1994)

Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network. - D. Jacquet; Gabriele Saucier (EDAC-ETC-EUROASIC, 1994)

The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. - Régis Leveugle; Zahava Koren; Israel Koren; Gabriele Saucier; Norbert Wehn (IEEE Trans. Computers, 1994)

Efficient synthesis of fault-tolerant controllers. - Raphaël Rochet; Régis Leveugle; Gabriele Saucier (ED&TC, 1995)

Design of defect-tolerant scan chains for MCMs with an active substrate. - P. Brahic; Régis Leveugle; Gabriele Saucier (DFT, 1995)

A Hierarchy-Driven FPGA Partitioning Method. - Helena Krupnova; Ali Abbara; Gabriele Saucier (DAC, 1997)

Synthesis and Floorplanning for Large Hierarchical FPGAs. - Helena Krupnova; Christian Rabedaoro; Gabriele Saucier (FPGA, 1997)

Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. - Bernard Laurent; Gilles Bosco; Gabriele Saucier (FPL, 1997)

Block and IP Wrapping for Efficient Design on FPGAs (Abstract). - Helena Krupnova; B. Behnam; Gabriele Saucier (FPGA, 1998)

Timing Driven Floorplanning on Programmable Hierarchical Targets. - S. A. Senouci; Aadil Amoura; Helena Krupnova; Gabriele Saucier (FPGA, 1998)

A Knowledge-Based System for Prototyping on FPFAs. - Helena Krupnova; Vu DucAnh Dinh; Gabriele Saucier (FPL, 1998)

Real Time Prototyping Method and a Case Study. - Helena Krupnova; Dinh Duc Anh Vu; Gabriele Saucier; Michel Boubal (International Workshop on Rapid System Prototyping, 1998)

Fast Arithmetic on Xilinx 5200 FPGA. - Bernard Laurent; Gilles Bosco; Gabriele Saucier (VLSI Design, 1998)

Using cone structures for circuit partitioning into FPGA packages. - Daniel R. Brasen; Gabriele Saucier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. - Helena Krupnova; Gabriele Saucier (DATE, 1999)

Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. - Helena Krupnova; Gabriele Saucier (FPGA, 1999)

Hierarchical Interactive Approach to Partition Large Designs into FPGAs. - Helena Krupnova; Gabriele Saucier (FPL, 1999)

FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. - Helena Krupnova; Christian Rabedaoro; Gabriele Saucier (IEEE International Workshop on Rapid System Prototyping, 1999)

FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. - Helena Krupnova; Gabriele Saucier (FPL, 2000)

FPGA Technology Snapshot: Current Devices and Design Tools. - Helena Krupnova; Gabriele Saucier (IEEE International Workshop on Rapid System Prototyping, 2000)

Who Owns the Platform? - Vassilios Gerousis; Oz Levia; Pierre G. Paulin; Mark Pinto; Chris Rowen; Gabriele Saucier (DATE, 2002)

E-Design Based on the Reuse Paradigm. - L. Ghanmi; A. Ghrab; M. Hamdoun; B. Missaoui; K. Skiba; Gabriele Saucier (DATE, 2002)