CAD methodology for Analog Static CMOS Design Automation. - Francois Rudolff; Edith Kussener; Gaëtan Bracmard (ICECS, 2007)

A PLL with loop bandwidth enhancement for low-noise and fast-settling clock recovery. - Julien Roche; Wenceslas Rahadjandrabe; Lahkdar Zady; Gaëtan Bracmard; Daniele Fronte (ICECS, 2008)