SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals. - Gaëtan Leplus; Olivier Savry; Lilian Bossuet (DSD, 2022)

Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor. - Gaëtan Leplus; Olivier Savry; Lilian Bossuet (HOST, 2022)