An Efficient Assertion Checker for Combinational Properties. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (DAC, 1997)

Load Balancing and Workload Minimization Of Overlapping Parallel Tasks. - Venkatram Krishnaswamy; Gagan Hasteer; Prithviraj Banerjee (ICPP, 1997)

Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors. - John G. Holm; John A. Chandy; Steven Parkes; Sumit Roy 003; Venkatram Krishnaswamy; Gagan Hasteer; Prithviraj Banerjee (International Conference on Supercomputing, 1997)

Simulated Annealing Based Parallel State Assignment of Finite State Machines. - Gagan Hasteer; Prithviraj Banerjee (J. Parallel Distributed Comput., 1997)

An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (DAC, 1998)

Efficient equivalence checking of multi-phase designs using retiming. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (ICCAD, 1998)

A Parallel Algorithm for State Assignment of Finite State Machines. - Gagan Hasteer; Prithviraj Banerjee (IEEE Trans. Computers, 1998)

Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (ACM Trans. Design Autom. Electr. Syst., 1998)

Efficient Equivalence Checking in a Modular Design Environment - Gagan Hasteer (1998)

Automatic Parallelization of Compiled Event Driven VHDL Simulation. - Venkatram Krishnaswamy; Gagan Hasteer; Prithviraj Banerjee (IEEE Trans. Computers, 2002)

Symbolic representation with ordered function templates. - Amit Goel; Gagan Hasteer; Randal E. Bryant (DAC, 2003)

Non-cycle-accurate sequential equivalence checking. - Pankaj Chauhan; Deepak Goyal; Gagan Hasteer; Anmol Mathur; Nikhil Sharma (DAC, 2009)