Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). - Pierre-Emmanuel Gaillardon; Gain Kim; Xifan Tang; Luca Gaetano Amarù; Giovanni De Micheli (FPGA, 2015)

Design optimization of polyphase digital down converters for extremely high frequency wireless communications. - Gain Kim; Raffaele Capoccia; Yusuf Leblebici (VLSI-SoC, 2015)

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells. - Pierre-Emmanuel Gaillardon; Xifan Tang; Gain Kim; Giovanni De Micheli (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links. - Gain Kim; Yusuf Leblebici (APCCAS, 2016)

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. - Kiarash Gharibdoust; Gain Kim; Armin Tajalli; Yusuf Leblebici (ISCAS, 2016)

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. - Gain Kim; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Study on the Programming Structures for RRAM-Based FPGA Architectures. - Xifan Tang; Gain Kim; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme. - Gain Kim; Thierry Barailler; Chen Cao; Kiarash Gharibdoust; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. - Gain Kim; Chen Cao; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl; et al. (ISCAS, 2018)

Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals. - Kyong Hwan Jin; Gain Kim; Yusuf Leblebici; Jong Chul Ye; Michael Unser (CoRR, 2018)

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (A-SSCC, 2019)

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (ISSCC, 2019)

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link. - Gain Kim; Woohyun Kwon; Thomas Toifl; Yusuf Leblebici; Hyeon-Min Bae (MWSCAS, 2019)

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. - Gain Kim; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Andreas Burg 001; Thomas Toifl; Yusuf Leblebici; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2020)

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators. - Jaewon Lee; Gain Kim; Jinho Park 004; Hyeon-Min Bae (ISCAS, 2021)

Bin-Specific Quantization in Spectral-Domain Convolutional Neural Network Accelerators. - Jinho Park 004; Jaewon Lee; Gain Kim; Hyeon-Min Bae (AICAS, 2022)

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications. - Gain Kim (IEEE Open J. Circuits Syst., 2022)

Does Charge Balancing Ensure the Safety of the Electrical Stimulation and Is It Power Efficientƒ. - Reza Ranjandish; Gain Kim (EMBC, 2023)

An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm. - Hanho Choi; Ha-Il Song; Hyosup Won; Jun Young Yoo; Woohyun Kwon; Huxian Jin; Konan Kwon; Cheong Min Lee; Gain Kim; Jake Eu; Sean Park; Hyeon-Min Bae (ESSCIRC, 2023)

A 1V-Supply $1.85 mathrm{V}_{ text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2nd-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS. - Geunha Kim; Sehwan Lee; Taeryoung Seol; Seungyeob Baik; Yeonjae Shin; Gain Kim; Jong-Hyeok Yoon; Arup K. George; Junghyup Lee (ISSCC, 2023)

Far-End Crosstalk Cancellation With MIMO OFDM for >200 Gb/s ADC-Based Serial Links. - Gain Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. - Jaehyun Lee; Dong-gu Choi; Minyoung Song; Gain Kim; Jong-Hyeok Yoon (CICC, 2024)

Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics. - Yujin Choi; Seoyoung Jang; Gain Kim (ICEIC, 2024)

A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator. - Seoyoung Jang; Jaewon Lee; Gain Kim (ICEIC, 2024)

DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects. - Seoyoung Jang; Jaewon Lee; Yujin Choi; Donggeon Kim; Gain Kim (ISCAS, 2024)

A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links. - Jaewon Lee; Seoyoung Jang; Yujin Choi; Donggeon Kim; Matthias Braendli; Marcel A. Kossel; Andrea Ruffino; Thomas Morf; Pier Andrea Francese; Gain Kim (ISCAS, 2024)

A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links. - Seoyoung Jang; Jaewon Lee; Yujin Choi; Donggeon Kim; Gain Kim (ISOCC, 2024)

A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links. - Jaewon Lee; Seoyoung Jang; Donggeon Kim; Yujin Choi; Sungyu Song; Gain Kim (ISOCC, 2024)

A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition. - Sehwan Lee; Taeryoung Seol; Geunha Kim; Minyoung Song; Gain Kim; Jong-Hyeok Yoon; Arup K. George; Junghyup Lee (VLSI Technology and Circuits, 2024)

Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links. - Myungguk Lee; Jaeik Cho; Junung Choi; Won Joon Choi; Jiyun Lee; Iksu Jang; Changjae Moon; Gain Kim; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform. - Jaewon Lee; Seoyoung Jang; Yujin Choi; Donggeon Kim; Serdar A. Yonar; Matthias Braendli; Andrea Ruffino; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links. - Woohyun Kwon; Hyosup Won; Taeho Kim; Sejun Jeon; Soon-Won Kwon; Ha-Il Song; Hanho Choi; Bongjin Kim; Huxian Jin; Jun-Gi Jo; Woosang Han; Tai-Young Kim; et al. (IEEE J. Solid State Circuits, 2024)

A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers. - Donggeon Kim; Yujin Choi; Jaewon Lee; Seoyoung Jang; Sungyu Song; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform. - Jaewon Lee; Seoyoung Jang; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC. - Jaewon Lee; Seoyoung Jang; Donggeon Kim; Yujin Choi; Jong-Hyeok Yoon; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Time-Domain Analysis, Modeling and Optimization of Analog Amplitude-Modulated Multi-Tone Serial Data Transceivers. - Donggeon Kim; Seongjin Kim; Gain Kim (ICEIC, 2025)

7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET. - Jaewon Lee; Pier Andrea Francese; Matthias Brändli; Thomas Morf; Marcel A. Kossel; Seoyoung Jang; Gain Kim (ISSCC, 2025)

A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization. - Hyoseok Song; Kwangmin Kim; Gain Kim; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)

BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. - Jaehyun Lee; Dong-gu Choi; Gain Kim; Minyoung Song; Jong-Hyeok Yoon (IEEE J. Solid State Circuits, 2025)

An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses. - Won Joon Choi; Myungguk Lee; Junung Choi; Jaeik Cho; Gain Kim; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform. - Jaewon Lee; Seoyoung Jang; Yujin Choi; Donggeon Kim; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)