Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. - Ganapathy Parthasarathy; Michael L. Bushnell (VTS, 1998)

Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. - Vishwani D. Agrawal; Michael L. Bushnell; Ganapathy Parthasarathy; Rajesh Ramadoss (VLSI Design, 1999)

An analysis of ATPG and SAT algorithms for formal verification. - Ganapathy Parthasarathy; Chung-Yang Huang; Kwang-Ting Cheng (HLDVT, 2001)

Interconnect Resource-Aware Placement for Hierarchical FPGAs. - Amit Singh 001; Ganapathy Parthasarathy; Malgorzata Marek-Sadowska (ICCAD, 2001)

Interconnect complexity-aware FPGA placement using Rent's rule. - Ganapathy Parthasarathy; Malgorzata Marek-Sadowska; Arindam Mukherjee 001; Amit Singh 001 (SLIP, 2001)

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. - Ganapathy Parthasarathy; Madhu K. Iyer; Tao Feng 012; Li-C. Wang; Kwang-Ting Cheng; Magdy S. Abadir (ITC, 2002)

Efficient circuit clustering for area and power reduction in FPGAs. - Amit Singh 001; Ganapathy Parthasarathy; Malgorzata Marek-Sadowska (ACM Trans. Design Autom. Electr. Syst., 2002)

A comparison of BDDs, BMC, and sequential SAT for model checking. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (HLDVT, 2003)

SATORI - A Fast Sequential SAT Engine for Circuits. - Madhu K. Iyer; Ganapathy Parthasarathy; Kwang-Ting Cheng (ICCAD, 2003)

Efficient reachability checking using sequential SAT. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (ASP-DAC, 2004)

An efficient finite-domain constraint solver for circuits. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (DAC, 2004)

Safety Property Verification Using Sequential SAT and Bounded Model Checking. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (IEEE Des. Test Comput., 2004)

Structural search for RTL with predicate learning. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Forrest Brewer (DAC, 2005)

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. - Madhu K. Iyer; Ganapathy Parthasarathy; Kwang-Ting Cheng (DATE, 2005)

An Efficient Sequential SAT Solver With Improved Search Strategies. - Feng Lu 002; Madhu K. Iyer; Ganapathy Parthasarathy; Li-C. Wang; Kwang-Ting Cheng; Kuang-Chien Chen (DATE, 2005)

RTL SAT simplification by Boolean and interval arithmetic reasoning. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Forrest Brewer (ICCAD, 2005)

Test Knowledge Data Base. - Arun Venkatachar; S. Rajakumar; M. Chapman; Sajeewan Basuru; Ganapathy Parthasarathy; C.-C. Lin; A. Hegde; T. Li (VLSI-DAT, 2017)

Resource Aware Scheduling for EDA Regression Jobs. - Saurav Nanda; Ganapathy Parthasarathy; Parivesh Choudhary; Arun Venkatachar (Euro-Par Workshops, 2019)

RTL Regression Test Selection using Machine Learning. - Ganapathy Parthasarathy; Aabid Rushdi; Parivesh Choudhary; Saurav Nanda; Malan Evans; Hansika Gunasekara; Sridhar Rajakumar (ASP-DAC, 2022)

Optimizing ML Classification Models for Constrained EDA Resource Budgets. - Ganapathy Parthasarathy; Bhuvnesh Kumar; Saurav Nanda; Parivesh Choudhary; Sridhar Rajakumar (ICCD, 2022)

Optimizing Constrained Random Verification with ML and Bayesian Estimation. - Bhuvnesh Kumar; Ganapathy Parthasarathy; Saurav Nanda; Sridhar Rajakumar (MLCAD, 2023)

HDL-GPT: High-Quality HDL is All You Need. - Bhuvnesh Kumar; Saurav Nanda; Ganapathy Parthasarathy; Pawan Patil; Austin Tsai; Parivesh Choudhary (CoRR, 2024)