Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits. - Ganesh C. Patil; Shafi Qureshi (ISVLSI, 2011)

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits. - Ganesh C. Patil; S. Qureshi (Microelectron. J., 2012)

Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits. - Ganesh C. Patil; Shafi Qureshi (Microelectron. Reliab., 2013)

Si3N4: HfO2 dual-k spacer bulk planar junctionless transistor for mixed signal integrated circuits. - Ramarao Garike; Ganesh C. Patil (IET Circuits Devices Syst., 2019)