Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. - Ritesh Rajore; Ganesh Garga; H. S. Jamadagni; S. K. Nandy 001 (ASAP, 2008)

Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. - Ganesh Garga; Mythri Alle; Keshavan Varadarajan; S. K. Nandy 001; H. S. Jamadagni (SoC, 2008)

High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. - Ganesh Garga; David Guevorkian; S. K. Nandy 001; H. S. Jamadagni (ICSAMOS, 2009)

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. - Ratna Krishnamoorthy; Keshavan Varadarajan; Ganesh Garga; Mythri Alle; S. K. Nandy 001; Ranjani Narayan; Masahiro Fujita (CASES, 2010)

A Method for Flexible Reduction over Binary Fields using a Field Multiplier. - Saptarsi Das; Keshavan Varadarajan; Ganesh Garga; Rajdeep Mondal; Ranjani Narayan; S. K. Nandy 001 (SECRYPT, 2011)

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). - Farhad Merchant; Anupam Chattopadhyay; Ganesh Garga; S. K. Nandy 001; Ranjani Narayan; Nandhini Gopalan (VLSID, 2014)