Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz (ICCD, 2003)

Defect Aware Test Patterns. - Huaxing Tang; Gang Chen 011; Sudhakar M. Reddy; Chen Wang 014; Janusz Rajski; Irith Pomeranz (DATE, 2005)

A unified fault model and test generation procedure for interconnect opens and bridges. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Piet Engelke; Bernd Becker 001 (ETS, 2005)

A test pattern ordering algorithm for diagnosis with truncated fail data. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (DAC, 2006)

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2006)

N-distinguishing Tests for Enhanced Defect Diagnosis. - Gang Chen 011; Janusz Rajski; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2009)