Coalescing Conditional Branches into Efficient Indirect Jumps. - Gang-Ryung Uh; David B. Whalley (SAS, 1997)

Improving Performance by Branch Reordering. - Minghui Yang; Gang-Ryung Uh; David B. Whalley (PLDI, 1998)

Effective Exploitation of a Zero Overhead Loop Buffer. - Gang-Ryung Uh; Yuhong Wang; David B. Whalley; Sanjay Jinturkar; Chris Burns; Vincent Cao (Workshop on Languages, Compilers, and Tools for Embedded Systems, 1999)

Effectively Exploiting Indirect Jumps. - Gang-Ryung Uh; David B. Whalley (Softw. Pract. Exp., 1999)

Techniques for Effectively Exploiting a Zero Overhead Loop Buffer. - Gang-Ryung Uh; Yuhong Wang; David B. Whalley; Sanjay Jinturkar; Chris Burns; Vincent Cao (CC, 2000)

Experience with a retargetable compiler for a commercial network processor. - Jinhwan Kim; Sungjoon Jung; Yunheung Paek; Gang-Ryung Uh (CASES, 2002)

Efficient and effective branch reordering using profile data. - Minghui Yang; Gang-Ryung Uh; David B. Whalley (ACM Trans. Program. Lang. Syst., 2002)

Branch Elimination via Multi-variable Condition Merging. - William C. Kreahling; David B. Whalley; Mark W. Bailey; Xin Yuan 001; Gang-Ryung Uh; Robert van Engelen (Euro-Par, 2003)

Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. - Gang-Ryung Uh (SCOPES, 2003)

Tuning the WCET of Embedded Applications. - Wankang Zhao; Prasad A. Kulkarni; David B. Whalley; Christopher A. Healy; Frank Mueller 001; Gang-Ryung Uh (IEEE Real-Time and Embedded Technology and Applications Symposium, 2004)

Code optimizations for a VLIW-style network processing unit. - Jinhwan Kim; Yunheung Paek; Gang-Ryung Uh (Softw. Pract. Exp., 2004)

Branch elimination by condition merging. - William C. Kreahling; David B. Whalley; Mark W. Bailey; Xin Yuan 001; Gang-Ryung Uh; Robert van Engelen (Softw. Pract. Exp., 2005)

Compiler transformations for effectively exploiting a zero overhead loop buffer. - Gang-Ryung Uh; Yuhong Wang; David B. Whalley; Sanjay Jinturkar; Yunheung Paek; Vincent Cao; Chris Burns (Softw. Pract. Exp., 2005)

Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs. - Doosan Cho; Ravi Ayyagari; Gang-Ryung Uh; Yunheung Paek (EUC Workshops, 2006)

Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. - Doosan Cho; Ravi Ayyagari; Gang-Ryung Uh; Yunheung Paek (CC, 2007)

Improving Low Power Processor Efficiency with Static Pipelining. - Ian Finlayson; Gang-Ryung Uh; David B. Whalley; Gary S. Tyson (Interaction between Compilers and Computer Architectures, 2011)

An Overview of Static Pipelining. - Ian Finlayson; Gang-Ryung Uh; David B. Whalley; Gary S. Tyson (IEEE Comput. Archit. Lett., 2012)

Improving processor efficiency by statically pipelining instructions. - Ian Finlayson; Brandon Davis; Peter Gavin; Gang-Ryung Uh; David B. Whalley; Magnus Själander; Gary S. Tyson (LCTES, 2013)

Scheduling instruction effects for a statically pipelined processor. - B. Davis; Ryan Baird; Peter Gavin; Magnus Själander; Ian Finlayson; F. Rasapour; G. Cook; Gang-Ryung Uh; David B. Whalley; Gary S. Tyson (CASES, 2015)

Optimizing Transfers of Control in the Static Pipeline Architecture. - Ryan Baird; Peter Gavin; Magnus Själander; David B. Whalley; Gang-Ryung Uh (LCTES, 2015)

Facilitating the Bootstrapping of a New ISA. - Abigail Mortensen; Scott Pomerville; David B. Whalley; Soner Önder; Gang-Ryung Uh (LCTES, 2023)