A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate. - Vandana Shukla; O. P. Singh; Ganga Ram Mishra; Raj Kumar Tiwari (Int. J. Bus. Data Commun. Netw., 2015)

Analysis and design of single ended SRAM cell for low-power operation. - Sunil Kumar Ojha; O. P. Singh; Ganga Ram Mishra; P. R. Vaya (ICIIS, 2016)

Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach. - Vandana Shukla; O. P. Singh; Ganga Ram Mishra; Raj Kumar Tiwari (ICIIS, 2016)

Realisation of optimised eight-bit binary shifter using reversible logic approach. - Vandana Shukla; O. P. Singh; Ganga Ram Mishra; Raj Kumar Tiwari (Int. J. Serv. Technol. Manag., 2017)

High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm. - Prashant Kumar; Prabhat Chandra Shrivastava; Manish Tiwari; Ganga Ram Mishra (Circuits Syst. Signal Process., 2019)

FPGA-based Hardware Classifier for Diabetic Sensorimotor Polyneuropathy Severity Assessment. - Sandeep Kumar Pandey; Geetika Srivastava; Mamun Bin Ibne Reaz; Sawal Hamid Md. Ali; Edi Kurniawan; Rabindra Gandhi Thangarajoo; Ganga Ram Mishra; Sacchidanand Shukla (AISD, 2023)