Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. - Youngchul Cho; Ganghee Lee; Kiyoung Choi; Sungjoo Yoo; Nacer-Eddine Zergainoh (Embedded Software for SoC, 2003)

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. - Youngchul Cho; Ganghee Lee; Sungjoo Yoo; Kiyoung Choi; Nacer-Eddine Zergainoh (DATE, 2003)

Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. - Ganghee Lee; Seokhyun Lee; Yongjin Ahn; Kiyoung Choi (ICSAMOS, 2007)

SoCDAL: System-on-chip design AcceLerator. - Yongjin Ahn; Keesung Han; Ganghee Lee; Hyunjik Song; Jun-hee Yoo; Kiyoung Choi; Xingguang Feng (ACM Trans. Design Autom. Electr. Syst., 2008)

Coarse-grained reconfigurable architecture for multiple application domains: a case study. - Manhwee Jo; Ganghee Lee; Kyungwook Chang; Kyuseung Han; Kiyoung Choi; Hoonmo Yang; Kiwook Yoon (ICHIT, 2009)

Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture. - Ganghee Lee; Kiyoung Choi (AHS, 2010)

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. - Ganghee Lee; Seokhyun Lee; Kiyoung Choi; Nikil D. Dutt (ARC, 2010)

Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. - Ganghee Lee; Kyungwook Chang; Kiyoung Choi (IPDPS Workshops, 2010)

Communication architecture design for reconfigurable multimedia SoC platform. - Ganghee Lee; Yongjin Ahn; Seokhyun Lee; Jeongki Son; Kiwook Yoon; Kiyoung Choi (Des. Autom. Embed. Syst., 2010)

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. - Ganghee Lee; Kiyoung Choi; Nikil D. Dutt (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture. - Kyuseung Han; Ganghee Lee; Kiyoung Choi (IEEE Trans. Dependable Secur. Comput., 2014)

TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS. - Ganghee Lee; Dimitris Agiakatsikas; Tong Wu 007; Ediz Cetin; Oliver Diessel (FCCM, 2017)

From C to Fault-Tolerant FPGA-Based Systems. - Dimitris Agiakatsikas; Ganghee Lee; Thomas Mitchell; Ediz Cetin; Oliver Diessel (FCCM, 2018)

Fault Recovery Time Analysis for Coarse-Grained Reconfigurable Architectures. - Ganghee Lee; Ediz Cetin; Oliver Diessel (ACM Trans. Embed. Comput. Syst., 2018)

Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems. - Zhuoran Zhao 002; Nguyen T. H. Nguyen; Dimitris Agiakatsikas; Ganghee Lee; Ediz Cetin; Oliver Diessel (ACM Trans. Reconfigurable Technol. Syst., 2018)