Highly Stackable 3D Ferroelectric NAND Devices: Beyond the Charge Trap Based Memory. - Sunghyun Yoon; Sung-In Hong; Garam Choi; Daehyun Kim; Ildo Kim; Seok Min Jeon; Changhan Kim; Kyunghoon Min (IMW, 2022)

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Donghun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (A-SSCC, 2023)

QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering. - Sunghyun Yoon; Sung-In Hong; Daehyun Kim; Garam Choi; Young Mo Kim; Kyunghoon Min; Seiyon Kim; Myung-Hee Na; Seonyong Cha (VLSI Technology and Circuits, 2023)

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Dong-Hun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (IEEE J. Solid State Circuits, 2024)