A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. - Nicky Chau-Chun Lu; Gary B. Bronner; Koji Kitamura; Roy E. Scheuerlein; Walter H. Henkels; Sang H. Dhong; Yasunao Katayama; Toshiaki Kirihata; Hideto Niijima; Robert L. Franch; Wei Wang; Motoo Nishiwaki; et al. (IEEE J. Solid State Circuits, 1989)

A 4-Mb low-temperature DRAM. - Walter H. Henkels; Duen-Shun Wen; Rick L. Mohler; Robert L. Franch; Thomas J. Bucelot; Christopher W. Long; John A. Bracchitta; W. J. Cote; Gary B. Bronner; Yuan Taur; Robert H. Dennard (IEEE J. Solid State Circuits, 1991)

Challenges and future directions for the scaling of dynamic random-access memory (DRAM). - Jack A. Mandelman; Robert H. Dennard; Gary B. Bronner; John K. DeBrosse; Rama Divakaruni; Yujun Li; Carl J. Raden (IBM J. Res. Dev., 2002)

Optimization of silicon technology for the IBM System z9. - Daniel J. Poindexter; Scott R. Stiffler; Philip T. Wu; Paul D. Agnello; Thomas Ivers; Shreesh Narasimha; Thomas B. Faure; Jed H. Rankin; David A. Grosch; Marc D. Knox; Daniel C. Edelstein; Mukesh Khare; et al. (IBM J. Res. Dev., 2007)