A technique for high-speed, fine-resolution pattern generation and its CMOS implementation. - Gary C. Moyer; Mark Clements; Wentai Liu; Toby Schaffer; Ralph K. Cavin III (ARVLSI, 1995)

High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique. - Gary C. Moyer; Mark Clements; Wentai Liu; Toby Schaffer; Ralph K. Cavin III (ISCAS, 1995)

The delay vernier pattern generation technique. - Gary C. Moyer; Mark Clements; Wentai Liu; Toby Schaffer; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1997)