A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. - Yen-Huei Chen; Gary Chan; Shao-Yu Chou; Hsien-Yu Pan; Jui-Jen Wu; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2009)

MixNStream: multi-source video distribution with stream mixers. - Philip Chun Ho Yuen; Gary Chan (AVSTP2P@MM, 2010)

Unified framework for multifactor authentication. - Christopher J. Pavlovski; Claudia Warwar; Brett Paskin; Gary Chan (ICT, 2015)

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (ISSCC, 2020)

A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology. - Nail Etkin Can Akkaya; Gary Chan; Hung-Jen Liao; Yih Wang; Jonathan Chang (VLSI Technology and Circuits, 2022)

The impact of eSports and online video gaming on lifestyle behaviours in youth: A systematic review. - Gary Chan; Yan Huo; Sarah Kelly; Janni Leung; Calvert Tisdale; Matthew Gullo (Comput. Hum. Behav., 2022)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)