Experience with building a commodity Intel-based ccNUMA system. - Bishop Brock; Gary D. Carpenter; Eli Chiprout; Mark E. Dean; Philippe L. De Backer; E. N. Elnozahy; Hubertus Franke; Mark Giampapa; David Glasco; James L. Peterson; Ramakrishnan Rajamony; Rajan Ravindran; et al. (IBM J. Res. Dev., 2001)

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. - Kevin J. Nowka; Gary D. Carpenter; Eric W. MacDonald; Hung C. Ngo; Bishop Brock; Koji I. Ishii; Tuyet Nguyen; Jeffrey L. Burns (IEEE J. Solid State Circuits, 2002)

Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. - Vikas Chandra; Gary D. Carpenter; Jeffrey L. Burns (ICCD, 2003)

The design and application of the PowerPC 405LP energy-efficient system-on-a-chip. - Kevin J. Nowka; Gary D. Carpenter; Bishop Brock (IBM J. Res. Dev., 2003)

A Scheme for On-Chip Timing Characterization. - Ramyanshu Datta; Gary D. Carpenter; Kevin J. Nowka; Jacob A. Abraham (VTS, 2006)

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. - Alan J. Drake; Robert M. Senger; Harmander Deogun; Gary D. Carpenter; Soraya Ghiasi; Tuyet Nguyen; Norman K. James; Michael S. Floyd; Vikas Pokala (ISSCC, 2007)

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. - Jente B. Kuang; Abraham Mathews; John Barth 001; Fadi H. Gebara; Tuyet Nguyen; Jeremy D. Schaub; Kevin J. Nowka; Gary D. Carpenter; Don Plass; Erik Nelson; Ivan Vo; William R. Reohr; et al. (ESSCIRC, 2008)

On-Chip Delay Measurement Based Response Analysis for Timing Characterization. - Ramyanshu Datta; Antony Sebastine; Ashwin Raghunathan; Gary D. Carpenter; Kevin J. Nowka; Jacob A. Abraham (J. Electron. Test., 2010)

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor. - Alan J. Drake; Michael S. Floyd; Richard L. Willaman; Derek J. Hathaway; Joshua Hernandez; Crystal Soja; Marshall D. Tiner; Gary D. Carpenter; Robert M. Senger (ISLPED, 2013)