Automation in the design of asynchronous sequential circuits. - Robert J. Smith 001; James H. Tracey; W. L. Schoeffel; Gary K. Maki (AFIPS Spring Joint Computing Conference, 1968)

Generation of Design Equations in Asynchronous Sequential Circuits. - Gary K. Maki; James H. Tracey; Robert J. Smith 001 (IEEE Trans. Computers, 1969)

State Assignment Selection in Asynchronous Sequential Circuits. - Gary K. Maki; James H. Tracey (IEEE Trans. Computers, 1970)

A State Assignment Procedure for Asynchronous Sequential Circuits. - Gary K. Maki; James H. Tracey (IEEE Trans. Computers, 1971)

Maximum-distance linear codes (Corresp.). - Gary K. Maki; James H. Tracey (IEEE Trans. Inf. Theory, 1971)

Improved State Assignment Selection Tests. - Gary K. Maki; Dwight H. Sawin III; Bore-Ren A. Jeng (IEEE Trans. Computers, 1972)

Comments on "Next-State Equations of Asynchronous Sequential Machines". - Gary K. Maki; Dwight H. Sawin III (IEEE Trans. Computers, 1973)

Fault-Tolerant Asynchronous Sequential Machines. - Gary K. Maki; Dwight H. Sawin III (IEEE Trans. Computers, 1974)

Asynchronous Sequential Machines Designed for Fault Detection. - Dwight H. Sawin III; Gary K. Maki (IEEE Trans. Computers, 1974)

Safe Asynchronous Sequential Circuits. - Ray S. Wickersham; Gary K. Maki (IEEE Trans. Computers, 1974)

Comments on "Fault-Tolerant Asynchronous Networks". - Dwight H. Sawin III; Gary K. Maki (IEEE Trans. Computers, 1975)

Fail-Safe Asynchronous Sequential Machines. - Dwight H. Sawin III; Gary K. Maki (IEEE Trans. Computers, 1975)

Pass-transistor asynchronous sequential circuits. - Sterling R. Whitaker; Gary K. Maki (IEEE J. Solid State Circuits, 1989)

VLSI asynchronous sequential circuit design. - Suresh K. Gopalakrishnan; Gary K. Maki (ICCD, 1990)

Sequence-invariant state machines. - Sterling R. Whitaker; Shamanna K. Manjunath; Gary K. Maki (IEEE J. Solid State Circuits, 1991)

Self Synchronized Asynchronous Sequential Pass Transistor Circuits. - Sterling R. Whitaker; Gary K. Maki (IEEE Trans. Computers, 1992)

An (8158, 7136) low-density parity-check encoder. - Lowell H. Miles; Jody W. Gambles; Gary K. Maki; William E. Ryan; Sterling R. Whitaker (CICC, 2005)

An 860-Mb/s (8158, 7136) Low-Density Parity-Check Encoder. - Lowell H. Miles; Jody W. Gambles; Gary K. Maki; William E. Ryan; Sterling R. Whitaker (IEEE J. Solid State Circuits, 2006)

Radiation Tolerance Techniques for a 1.6 Gb/s, 8 K and 4 K Low-Density Parity-Check Encoder. - Sterling R. Whitaker; Lowell H. Miles; Jody W. Gambles; Paul Winterrowd; Ron Nelson; Chad Orbe; Gary K. Maki (IEEE J. Solid State Circuits, 2009)