Accelerating Architectural Simulation by Parallel Execution of Trace Samples. - Gary Lauterbach (HICSS (1), 1994)

Low Load Latency Through Sum-Addressed Memory (SAM). - William L. Lynch; Gary Lauterbach; Joseph I. Chamdani (ISCA, 1998)

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. - Raymond A. Heald; Ken Shin; Vinita Reddy; I-Feng Kao; Masood Khan; William L. Lynch; Gary Lauterbach; Joe Petolino (IEEE J. Solid State Circuits, 1998)

Vying for the Lead in High-Performance Processors (Interview). - Gary Lauterbach (Computer, 1999)

UltraSPARC-III: designing third-generation 64-bit performance. - Tim Horel; Gary Lauterbach (IEEE Micro, 1999)

A third-generation SPARC V9 64-b microprocessor. - Raymond A. Heald; Kathirgamar Aingaran; Chaim Amir; Michael Ang; Michael Boland; Pankaj Dixit; Gary Gouldsberry; Dale Greenley; Joel Grinberg; Jason M. Hart; Tim Horel; Wen-Jay Hsu; et al. (IEEE J. Solid State Circuits, 2000)

Robust Highly-Connected Direct Interconnection Network Topologies. - Ilya Sharapov; Gary Lauterbach; Stephen P. Crago (PDPTA, 2003)

Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication. - Robert J. Drost; Craig Forrest; Bruce Guenin; Ron Ho; Ashok V. Krishnamoorthy; Danny Cohen; John E. Cunningham; Bernard Tourancheau; Arthur Zingher; Alex Chow; Gary Lauterbach; Ivan E. Sutherland (Hot Interconnects, 2005)

SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips. - Ashutosh Dhodapkar; Gary Lauterbach; Sean Lie; Dhiraj Mallick; Jim Bauman; Sundar Kanthadai; Toru Kuzuhara; Gene Shen; Min Xu; Chris Zhang (Hot Chips Symposium, 2011)

A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O. - Kshitij Sudan; Saisanthosh Balakrishnan; Sean Lie; Min Xu; Dhiraj Mallick; Gary Lauterbach; Rajeev Balasubramonian (HPCA, 2013)

The Path to Successful Wafer-Scale Integration: The Cerebras Story. - Gary Lauterbach (IEEE Micro, 2021)