Embedded DRAM built in self test and methodology for test insertion. - Peter Jakobsen; Jeffrey H. Dreibelbis; Gary Pomichter; Darren Anand; John Barth 001; Michael R. Nelms; Jeffrey Leach; George M. Belansek (ITC, 2001)

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. - John E. Barth Jr.; Jeffrey H. Dreibelbis; Eric A. Nelson; Darren Anand; Gary Pomichter; Peter Jakobsen; Michael R. Nelms; Jeffrey Leach; George M. Belansek (IBM J. Res. Dev., 2002)

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. - John E. Barth Jr.; Darren Anand; Steve Burns 001; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Michael R. Nelms; Erik Nelson; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Stephen Sliva (IEEE J. Solid State Circuits, 2005)

Low Cost Test of High Bandwidth Embedded Memories. - Kevin W. Gorman; Darren Anand; Gary Pomichter; William R. Corbin (CICC, 2006)

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. - Darren Anand; Jim Covino; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Mark Jacunski; Jake Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2007)

Advancements in at-speed array BIST: multiple improvements. - Kevin W. Gorman; Michael Roberge; Adrian Paparelli; Gary Pomichter; Stephen Sliva; William Corbin (ITC, 2007)

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. - Mark Jacunski; Darren Anand; Robert Busch; John A. Fifield; Matthew Lanahan; Paul Lane; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2010)