Random Pattern Testability. - Jacob Savir; Gary S. Ditlow; Paul H. Bardell (IEEE Trans. Computers, 1984)

HLSIM - A New Hierarchical Logic Simulator and Netlist Converter. - David A. Zein; Oliver P. Engel; Gary S. Ditlow (DAC, 1992)

Algorithms for the design verification of bipolar array chips. - David A. Zein; Oliver P. Engel; Gary S. Ditlow (VTS, 1992)

HLSIM-a new hierarchical logic simulator in APL. - David A. Zein; Oliver P. Engel; Gary S. Ditlow (VTS, 1992)

Parallel Analysis of IC Power Distribution Networks. - Gary S. Ditlow; Anshul Gupta; Richard L. Moore; David Moran; Ralph Williams; Tom Wilkins (PP, 1999)

Integrated Manufacturing and Development (IMaD). - David Moran; Gary S. Ditlow; Daria Dooling; Ralph Williams; Tom Wilkins (SC, 1999)

Structured and tuned array generation (STAG) for high-performance random logic. - Matthew M. Ziegler; Gary S. Ditlow; Stephen V. Kosonocky; Zhenyu Qi 001; Mircea R. Stan (ACM Great Lakes Symposium on VLSI, 2007)

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. - Gary S. Ditlow; Robert K. Montoye; Salvatore N. Storino; Sherman M. Dance; Sebastian Ehrenreich; Bruce M. Fleischer; Thomas W. Fox; Kyle M. Holmes; Junichi Mihara; Yutaka Nakamura; Shohji Onishi; Robert Shearer; et al. (ISSCC, 2011)