Electronic Process Limited Yield. - Gary W. Maier; Shawn Smith (ISQED, 2000)

A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias. - Matt Wordeman; Joel Silberman; Gary W. Maier; Michael Scheuermann (ISSCC, 2012)

A shorted global clock design for multi-GHz 3D stacked chips. - Liang-Teck Pang; Phillip J. Restle; Matthew R. Wordeman; Joel A. Silberman; Robert L. Franch; Gary W. Maier (VLSIC, 2012)

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. - Toshiaki Kirihata; John Golz; Matthew R. Wordeman; Pooja Batra; Gary W. Maier; Norman Robson; Troy L. Graves-abe; Daniel Berger; Subramanian S. Iyer (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)