Impact of quantum modulation of the inversion charge in the MOSFET subthreshold regime. - Gaspard Hiblot; Quentin Rafhay; Frédéric Boeuf; Gérard Ghibaudo (ESSDERC, 2014)

Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR. - Gaspard Hiblot; Quentin Rafhay; Loic Gaben; Gérard Ghibaudo; Frédéric Boeuf (ESSDERC, 2015)

Impact of short-channel effects on velocity overshoot in MOSFET. - Gaspard Hiblot; Quentin Rafhay; Frédéric Boeuf; Gérard Ghibaudo (NEWCAS, 2015)

Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage. - Gaspard Hiblot; Yefan Liu; Geert Hellings; Geert Van der Plas (IRPS, 2019)

Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending. - Yefan Liu; Hao Yu; Gaspard Hiblot; Anastasiia Kruv; Marc Schaekers; Naoto Horiguchi; Dimitrios Velenis; Ingrid De Wolf (IRPS, 2019)

Process-induced charging damage in IGZO nTFTs. - Gaspard Hiblot; Nouredine Rassoul; Lieve Teugels; Katia Devriendt; Adrian Vaisman Chasin; Michiel J. van Setten; Attilio Belmonte; Romain Delhougne; Gouri Sankar Kar (IRPS, 2021)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

NPN Si/SiGe memory selector with non-linearity>105 and ON-current>6MA/cm2. - Gaspard Hiblot; Taras Ravsher; Roger Loo; Bhuvaneshwari Yengula Venkata Ramana; Nathali Franchina-Vergel; Andrea Fantini; Shamin Houshmand Sharifi; Nina Bazzazian; Kurt Wostyn; Loris Angelo Labbate; Sebastien Couet; Gouri Sankar Kar (ESSDERC, 2023)

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). - Subrat Mishra; Sankatali Venkateswarlu; Bjorn Vermeersch; Moritz Brunion; Melina Lofrano; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Gaspard Hiblot; Geert Van der Plas; Pieter Weckx; et al. (IRPS, 2023)

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. - S. Yang; Pieter Schuddinck; Marie Garcia Bardon; Yang Xiang; Anabela Veloso; B. T. Chan; Gioele Mirabelli; Gaspard Hiblot; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2023)