A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology. - Ragh Kuttappa; Vinayak Honkote; Amreesh Rao; Gaurav Kamalkar; Kailash Chandrashekar; Eric Finley; Chaitanya Sankuratri; Faran Rafiq; Robert Orton; Nils Hernandez; Anuradha Srinivasan; Tanay Karnik (IEEE Solid State Circuits Lett., 2025)