Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms. - Ananth Somayaji Goda; Gautam Kapila (ISQED, 2005)

Reliability improvement of logic and clock paths in power-efficient designs. - Senthil Arasu; Mehrdad Nourani; Vijay Reddy; John M. Carulli Jr.; Gautam Kapila; Min Chen 024 (ACM J. Emerg. Technol. Comput. Syst., 2014)