Injection-lock dynamics in non-harmonic oscillators. - G. Reddy Gangasani; Peter R. Kinget (ISCAS, 2006)

A Time-Domain Model for Predicting the Injection Locking Bandwidth of Nonharmonic Oscillators. - G. Reddy Gangasani; Peter R. Kinget (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Time-Domain Model for Injection Locking in Nonharmonic Oscillators. - G. Reddy Gangasani; Peter R. Kinget (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)

A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS. - Gautam R. Gangasani; Peter R. Kinget (ESSCIRC, 2018)

A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS. - Gautam R. Gangasani; Peter R. Kinget (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS. - Gautam Reddy Gangasani; D. Hanson; Daniel W. Storaska; H. H. Xu; M. Kelly; M. Shannon; Michael Sorna; Michael Wielgos; P. B. Ramakrishna; S. Shi; S. Parker; U. K. Shukla; et al. (ISSCC, 2022)

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. - Gautam R. Gangasani; A. Mostafa; A. Singh; Daniel W. Storaska; D. Prabakaran; K. Mohammad; Matthew Baecher; M. Shannon; Michael Sorna; Michael Wielgos; P. Jenkins; P. B. Ramakrishna; et al. (VLSI Technology and Circuits, 2024)