Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. - Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin 001; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; Madhavan Swaminathan; et al. (DAC, 2019)

RTL-to-GDS Design Tools for Monolithic 3D ICs. - Jinwoo Kim; Gauthaman Murali; Pruek Vanna-Iampikul; Edward Lee; Daehyun Kim 004; Arjun Chaudhuri; Sanmitra Banerjee; Krishnendu Chakrabarty; Saibal Mukhopadhyay; Sung Kyu Lim (ICCAD, 2020)

Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. - Brian Crafton; Samuel Spetalnick; Gauthaman Murali; Tushar Krishna; Sung Kyu Lim; Arijit Raychowdhury (VLSI-SOC, 2020)

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. - Brian Crafton; Samuel Spetalnick; Gauthaman Murali; Tushar Krishna; Sung Kyu Lim; Arijit Raychowdhury (VLSI-SoC (Selected Papers), 2020)

Advances in Design and Test of Monolithic 3-D ICs. - Arjun Chaudhuri; Sanmitra Banerjee; Heechun Park; Jinwoo Kim; Gauthaman Murali; Edward Lee; Daehyun Kim 002; Sung Kyu Lim; Saibal Mukhopadhyay; Krishnendu Chakrabarty (IEEE Des. Test, 2020)

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. - Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin 001; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nael Mizanur Rahman; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies. - Gauthaman Murali; Sung Kyu Lim (DATE, 2021)

ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs. - Sanmitra Banerjee; Arjun Chaudhuri; Jinwoo Kim; Gauthaman Murali; Mark Nelson 005; Sung Kyu Lim; Krishnendu Chakrabarty (ICCAD, 2021)

Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems. - Gauthaman Murali; Heechun Park; Eric Qin 001; Hakki Mert Torun; Majid Ahadi Dolatsara; Madhavan Swaminathan; Tushar Krishna; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM. - Gauthaman Murali; Xiaoyu Sun 001; Shimeng Yu; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs. - Gauthaman Murali; Sandra Maria Shaji; Anthony Agnesina; Guojie Luo; Sung Kyu Lim (ISPD, 2022)

Design Automation and Test Solutions for Monolithic 3D ICs. - Lingjun Zhu; Arjun Chaudhuri; Sanmitra Banerjee; Gauthaman Murali; Pruek Vanna-Iampikul; Krishnendu Chakrabarty; Sung Kyu Lim (ACM J. Emerg. Technol. Comput. Syst., 2022)

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs. - Yi-Chen Lu; Sai Pentapati; Lingjun Zhu; Gauthaman Murali; Kambiz Samadi; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators. - Gauthaman Murali; Aditya Iyer 001; Navneeth Ravichandran; Sung Kyu Lim (ICCAD, 2023)

A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers. - Gauthaman Murali; Anthony Agnesina; Sung Kyu Lim (ACM Trans. Design Autom. Electr. Syst., 2023)

On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs. - Gauthaman Murali; Aditya Iyer 001; Lingjun Zhu; Jianming Tong; Francisco Muñoz-Martínez; Srivatsa Rangachar Srinivasa; Tanay Karnik; Tushar Krishna; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs. - Lingjun Zhu; Jiawei Hu; Gauthaman Murali; Sung Kyu Lim (ISLPED, 2024)

Design Methodology And Electronic Design Automation Techniques For Heterogeneous 3D Machine Learning Accelerators. - Gauthaman Murali (2024)

A High-Performance Passive Base System for Distributed AI/Media Acceleration. - Ragh Kuttappa; Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Paolo A. Aseron; Gauthaman Murali; Vinayak Honkote; Prerna Budhkar; Dileep Kurian; Ronald Kalim; Thomas P. Thomas; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. - Srivatsa Rangachar Srinivasa; Prerna Budhkar; Gauthaman Murali; Vui Seng Chua; Paolo A. Aseron; Vinayak Honkote; Ravi R. Iyer 001; Nilesh Jain; Dileep John Kurian; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators. - Gauthaman Murali; Min Gyu Park; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2025)