A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. - Samuel Leshner; Krzysztof S. Berezowski; Xiaoyin Yao; Gayathri Chalivendra; Saurabh Patel; Sarma B. K. Vrudhula (ISVLSI, 2010)

A new balanced 4-moduli set {2k, 2n - 1, 2n + 1, 2n+1-1} and its reverse converter design for efficient fir filter implementation. - Gayathri Chalivendra; Vinay Hanumaiah; Sarma B. K. Vrudhula (ACM Great Lakes Symposium on VLSI, 2011)