A novel design of leading zero anticipation circuit with parallel error detection. - Ge Zhang 007; Zichu Qi; Weiwu Hu (ISCAS (1), 2005)

Parallel Error Detection for Leading Zero Anticipation. - Ge Zhang 007; Weiwu Hu; Zichu Qi (J. Comput. Sci. Technol., 2006)

Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. - Xiaotao Chang; Mingming Zhang; Ge Zhang 007; Zhimin Zhang; Jun Wang (ISCAS, 2007)

An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects. - Jun Wang; Ge Zhang 007; Weiwu Hu (ISCAS, 2007)

Reducing cache energy consumption by tag encoding in embedded processors. - Mingming Zhang; Xiaotao Chang; Ge Zhang 007 (ISLPED, 2007)

Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor. - Jun Wang; Hongbo Zeng; Kun Huang; Ge Zhang 007; Yan Tang (DATE, 2008)

An interconnect-aware power efficient cache coherence protocol for CMPs. - Hongbo Zeng; Jun Wang; Ge Zhang 007; Weiwu Hu (IPDPS, 2008)

A synchronized variable frequency clock scheme in chip multiprocessors. - Qifei Fan; Ge Zhang 007; Weiwu Hu (ISCAS, 2008)

Optimizing power and throughput for m-out-of-n encoded asynchronous circuits. - Jun Xu; Ge Zhang 007; Weiwu Hu (ISQED, 2010)

Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. - Zichu Qi; Qi Guo 001; Ge Zhang 007; Xiangku Li; Weiwu Hu (VLSI Design, 2010)