Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration. - Wen-Yi Chen; Ming-Dou Ker; Yeh-Jen Huang; Yeh-Ning Jou; Geeng-Lih Lin (APCCAS, 2008)

Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection. - Wen-Yi Chen; Ming-Dou Ker; Yeh-Ning Jou; Yeh-Jen Huang; Geeng-Lih Lin (ISCAS, 2009)

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. - Seian-Feng Liao; Kai-Neng Tang; Ming-Dou Ker; Jia-Rong Yeh; Hwa-Chyi Chiou; Yeh-Jen Huang; Chun-Chien Tsai; Yeh-Ning Jou; Geeng-Lih Lin (ECCTD, 2015)

Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. - Chao-Yang Chen; Jian-Hsing Lee; Karuna Nidhi; Tzer-Yaa Bin; Geeng-Lih Lin; Ming-Dou Ker (IRPS, 2021)